Supports high performance system speed - from 66MHz to
133MHz
ZBT
TM
Feature - No dead cycles between write and read
cycles
Smart ZBT
TM
Feature - Eases system timing requirements
and reduces the likelihood of bus contention
With Smart ZBT
TM
the output turn-on (t
CLZ
) is adaptable to
the user's system and is a function of the cycle time
Backward compatible with IDT's existing ZBT offerings
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
W
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
BW
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (V
DDQ)
Packaged in a JEDEC standard 100-lead plastic thin quad
flatpack (TQFP) and 119-lead ball grid array (BGA).
Preliminary
IDT71V3566
IDT71V3568
x
x
Description
The IDT71V3566/68 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMs. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
TM
, or
Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3566/68 offer the user a Smart functionality which simplifies
system timing requirements when turning the bus around between writes
and reads. Traditionally, SRAMs are designed with fast turn-on times
(t
CLZ
) in order to meet the requirements of high speed applications. This
fast turn-on may lead to bus contention at slower speeds, i.e. 133 MHz and
slower, since these designs often use less aggressive ASICs/controllers
with loose turn-off parameters (t
CHZ
). Thus at slower speeds, more margin
on the RAM's t
CLZ
may be needed to compensate for the slow turn-off of
the ASIC/controller. The IDT71V3566/68 have the ability to provide this
extra margin by allowing t
CLZ
to adapt to the user's system.
With the Smart ZBT
TM
feature, the output turn-on time (t
CLZ
) adapts to
the user's system and is solely a function of cycle time (t
CYC
). Thus with
Smart ZBT
TM
, t
CLZ
is independent of process, voltage, and temperature
variations. With this deterministic output turn-on feature, the guesswork of
when the SRAM begins to drive the bus is removed, therefore easing
x
x
x
x
x
x
x
x
x
x
x
x
x
Pin Description Summary
A
0
-A
1 7
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
A DV /LD
LBO
I/O
0
-I/O
3 1
, I/O
P 1
-I/O
P 4
V
DD
, V
DDQ
V
SS
A d d re s s Inp uts
Chip E nab le s
Outp ut E nab le
Re ad /W rite S ig nal
Clo c k E nab le
Ind ivid ual B y te W rite S e le cts
Clo ck
A d v anc e b urst ad d re ss / Lo ad ne w ad d re ss
Line ar / Inte rle av e d B urs t Ord e r
Data Inp ut / Outp ut
Co re P o we r, I/O P o we r
Gro und
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
I/O
S up p ly
S up p ly
S ynchro no us
S ynchro no us
A s ync hro no us
S ynchro no us
S ynchro no us
S ynchro no us
N/A
S ynchro no us
S tatic
S ynchro no us
S tatic
S tatic
5295 tbl 01
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
Smart ZBT and Smart Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is also supported by Micron Technology, Inc.
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