HD66137T
High-Voltage Durable 240-Channel Common Driver
for Dot-Matrix STN LCD
ADE-207-291(Z)
Rev. 2
Aug. 03, 1999
Description
The HD 66137T is a 240-channel common driver which drives a dot matrix STN LCD panel. By changing
the mode, this can be applied to 240- and 200- and 160- channel output. Through the use of a 43-V high-
voltage CMOS process technology, a high-voltage drive of +21.5 V and –21.5 V, centering on VM is
possible. –21.5V generated from +21.5 V with built-in switching circuit and external capacity. Low logic-
drive voltage (3 V) is used. This device is used together with the segment driver HD66130, HD66134ST or
HD66136.
Features
•
•
•
•
•
•
•
•
Display duty: Up to 1/240
LCD drive voltage: 43 V max
Built-in switching circuit (to generate –21.5 V)
Number of LCD drive circuit: 240
Operating voltage: 2.5 to 5.5 V
Intermediate voltage I/F
Built-in alternating signal generation circuit Pin programmable
Output mode change: 240-output mode
200-output mode
160-output mode
•
Built-in display-off function
•
Flex TCP
1
2
1
2
3
4
5
X1
X2
X3
X4
X5
Top view
Note: The shape above does not indicate the actual outline.
236
237
238
239
240
X236
X237
X238
X239
X240
VLCDL
VHL
VML
VLL
VEEL
VEO
C1
C2
DIO2
M
RESET
MWS4
MWS3
MWS2
MWS1
MWS0
VCC
MODE1
MODE0
DOC
DISPOFF
AMP
SHL
GND
CL
CCL
M/S
DIO1
VEER
VLR
VMR
VHR
VLCDR
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258
257
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
HD66137T
Pin Arrangement
HD66137T
Block Diagram
X1—X240
*2, *3
VHL
VLL
VML
*1, *3
VLCDL,R
VEEL,R
VCC
GND
Shift register
D
Q
SR
SR
1
20
Q
φ
φ
D
Shift register
D
Q
SR
SR
21
40
Q
φ
φ
D
LCD drive circuit
Level
shifter
VHR
VLR
VMR
Level shifter
Logic
Logic
Logic
Logic
Logic
Shift register
D
Q
SR
SR
41
200
Q
φ
φ
D
Shift register
D
Q
SR
SR
201 220
Q
φ
φ
D
Shift register
D
Q
SR
SR
221 240
Q
φ
φ
D
DISPOFF
Logic
M/S
Switch circuit
Logic
Alternating signal
generating circuit
DIO1
DIO2
SHL
MODE0
MODE1
CL
VEO
CCL
AMP
C2
C1
M
*1
VLCDL and VLCDR, and VEEL and VEER are internally connected.
*2
VHL and VHR, VLL and VLR, and VML and VMR are internally connected.
DOC
MWS 0 to MWS 4
RESET
Logic
3
HD66137T
Internal Block Diagram
1. LCD drive Circuit
This circuit selects and outputs the three level signals for the LCD drive. By a combination of the data in
the shift register and M, either VH, VL, or VM is selected and transmitted to the output circuit.
2. Level shifter
This boosts a 5-V signal to a high-voltage signal for LCD drive.
3. Shift register
This is a 240-bit bidirectional shift register circuit. The first line marker signal output from the DIO1 pin
and DIO2 pin is sequentially shifted by shift clock CL. The shift direction is determined by the SHL pin.
4. Alternating signal generating circuit
This circuit generates an alternating signal (M signal) for LCD display. To suppress cross-talk, the signal is
alternated in a unit from several lines to several tens of lines. By connecting MWS0 to MWS4 pins to V
CC
or GND, the desired number of signals can be alternated. When alternating signals are externally input, all
pins (MWS0 to MWS4) are connected to GND.
HIFAS Family timing Comparison
HD66130/131S/134S/135/136
CL1
M
HD66132/133
Input
signal
Output
signal
Segment
Common
4
HD66137T
Pin Function
Classification
Power supply
Symbol
VLCDL, R
VEEL, R
V
CC
,
GND
VHL, R
VLL, R
VML, R
Connected
Pin No. to
273, 241 Power
269, 245 supply
257
250
272, 242 Power
270, 244 supply
271, 243
I/O
—
Functions
VLCDL, R–VEEL, R : Power supply for LCD
drive
VLCDL, R : Power supply for switch circuit
V
CC
–GND : Power supply for logic circuit
Power supply for LCD drive level
VHL, R : Selected level (Set to the same
voltage as VLCDL, R.)
VLL, R : Selected level (Set to the same
voltage as VEEL, R.)
VML, R : Non-selected level and Power
supply for switch circuit
output
When use built -in switching circuit and
generate VEE, VEO pin connect to VEEL, R
pins. VM voltage is point of reference and
reversed and output the voltage input to the
voltage between VLCD and VM. If built-in
switching circuit is not used, don't connect
any lines to this pin.
External capacitance should be connected
here when using the switch circuit for
generate VEE.
If built-in switching circuit is not used, don't
connect any lines to this pin.
Shift clock input. Data is shifted at the falling
edge of shift clock CL of the shift register.
Inputs or outputs the alternating current for
LCD drive output.
This pin specifies the cycle of the alternating
signal (M signal) in the unit of the number of
lines. The number of lines, which is an
integer from 2 to 31, is specified as follows.
Usually, specify the number of lines within a
range from 10 to 31. When the HD66131T is
driven by an external alternating signal,
specify the number of lines as zero.
Number MWS4 MWS3 MWS2 MWS1 MWS0
of lines
0
0
0
0
0
0
0
1
0
0
0
1
0
2
0
0
1
0
0
3
0
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
1
31
1
1
1
1
Line alternating
M-pin status
waveform
——
Input
Prohibited
Output
2 lines alternated
3 lines alternated
•
•
31 lines alternated
Input
VEO
268
VEEL, R
C1, C2
267, 266 Capacitance —
Control signal
CL
M
249
264
MPU
Extension
driver or
MPU
—
Input
I/O
MWS0
MWS1
MWS2
MWS3
MWS4
258
259
260
261
262
Input
5
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