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IDT72P51769L5BB8: 产品描述FIFO, 128KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256; 产品类别存储存储; 文件大小804KB，共87页; 制造商IDT (Integrated Device Technology)

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IDT72P51769L5BB8概述

FIFO, 128KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256

IDT72P51769L5BB8规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	BGA
包装说明	17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
针数	256
Reach Compliance Code	not_compliant
ECCN代码	EAR99
最长访问时间	3.6 ns
最大时钟频率 (fCLK)	200 MHz
周期时间	5 ns
JESD-30 代码	S-PBGA-B256
JESD-609代码	e0
长度	17 mm
内存密度	4718592 bit
内存集成电路类型	OTHER FIFO
内存宽度	36
湿度敏感等级	3
功能数量	1
端子数量	256
字数	131072 words
字数代码	128000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	128KX36
可输出	YES
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA256,16X16,40
封装形状	SQUARE
封装形式	GRID ARRAY
并行/串行	PARALLEL
电源	1.8 V
认证状态	Not Qualified
座面最大高度	3.5 mm
最大待机电流	0.1 A
最大压摆率	0.15 mA
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn63Pb37)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
宽度	17 mm

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1.8V MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 36 BIT WIDE CONFIGURATION

1,179,648 bits

2,359,296 bits

4,718,592 bits

ADVANCE INFORMATION

IDT72P51749

IDT72P51759

IDT72P51769

FEATURES

•

Choose from among the following memory density options:

IDT72P51749



Total Available Memory = 1,179,648 bits

IDT72P51759



Total Available Memory = 2,359,296 bits

IDT72P51769



Total Available Memory = 4,718,592 bits

Configurable from 1 to 128 Queues

Default configuration of 128 or 64 symmetrical queues

Default multi-queue device configurations

– IDT72P51749: 256 x 36 x 128Q

– IDT72P51759: 512 x 36 x 128Q

– IDT72P51769: 1,024 x 36 x 128Q

Default configuration can be augmented via the queue address

bus

Number of queues and individual queue sizes may be

configured at master reset though serial programming

200 MHz High speed operation (5ns cycle time)

3.6ns access time

Independent Read and Write access per queue

•

User Selectable Bus Matching Options:

– x36 in to x36 out

– x18 in to x36 out

– x9 in to x36 out

– x36in to x18out

– x18 in to x18 out

– x9 in to x18 out

– x36in to x9out

– x18 in to x9 out

– x9 in to x9 out

User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL

100% Bus Utilization, Read and Write on every clock cycle

Selectable First Word Fall Through (FWFT) or IDT standard

mode of operation

Ability to operate on packet or word boundaries

Mark and Re-Write operation

Mark and Re-Read operation

Individual, Active queue flags (OR /

EF, IR

FF, PAE, PAF, PR)

8 bit parallel flag status on both read and write ports

Direct or polled operation of flag status bus

Expansion of up to 256 queues

JTAG Functionality (Boundary Scan)

Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

HIGH Performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

FUNCTIONAL BLOCK DIAGRAM

MULTI-QUEUE FLOW-CONTROL DEVICE

WADEN

FSTR

WRADD

WEN

WCLK

WCS

READ CONTROL

Q127

RADEN

ESTR

RDADD

WRITE CONTROL

Q126

REN

RCLK

RCS

Q125

Din

Qout

x36, 18 or x9

DATA IN

x36, x18 or x9

DATA OUT

READ FLAGS

EF/OR

PAE

PAEn

WRITE FLAGS

FF/IR

PAF

PAFn

PRn

6714 drw01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2004

SEPTEMBER 2004

DSC-6714/-

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Table of Contents

Features ........................................................................................................................................................................................................................ 1

Description ................................................................................................................................................................................................................... 5

Pin configuration ......................................................................................................................................................................................................... 7

Detailed description .................................................................................................................................................................................................... 8

Pin descriptions ......................................................................................................................................................................................................... 10

Pin number table ........................................................................................................................................................................................................ 16

Recommended DC operating conditions ................................................................................................................................................................ 17

Absolute maximum ratings ........................................................................................................................................................................................ 17

DC electrical characteristics ..................................................................................................................................................................................... 18

AC electrical characteristics ...................................................................................................................................................................................... 20

Functional description .............................................................................................................................................................................................. 22

Serial Programming .............................................................................................................................................................................................. 23

Default Programming ............................................................................................................................................................................................ 23

Parallel Programming ........................................................................................................................................................................................... 23

Queue description ..................................................................................................................................................................................................... 25

Configuration of the IDT Multi-queue flow-control device ....................................................................................................................................... 25

Standard mode operation ..................................................................................................................................................................................... 26

Read Queue Selection and Read Operation ......................................................................................................................................................... 27

Switching Queues on the Write Port ...................................................................................................................................................................... 29

Switching Queues on the Read Port ..................................................................................................................................................................... 31

Flag description ......................................................................................................................................................................................................... 42

PAFn

Flag Bus Operation .................................................................................................................................................................................... 42

Full Flag Operation ............................................................................................................................................................................................... 42

Empty or Output Ready Flag Operation (EF/OR) .................................................................................................................................................. 42

Almost Full Flag .................................................................................................................................................................................................... 43

Almost Empty Flag ................................................................................................................................................................................................ 43

Packet Ready Flag ............................................................................................................................................................................................... 47

Packet Mode Demarcation bits .............................................................................................................................................................................. 49

JTAG Interface ............................................................................................................................................................................................................ 82

JTAG AC electrical characteristics ............................................................................................................................................................................ 86

Ordering Information ................................................................................................................................................................................................. 87

List of Tables

Table 1 — Device programming mode comparison ........................................................................................................................................................ 22

Table 2 — Setting the queue programming mode during master reset ............................................................................................................................. 22

Table 3 — Mode Configuration ...................................................................................................................................................................................... 25

Table 4 — Write Address Bus, WRADD[7:0] ................................................................................................................................................................... 26

Table 5 — Read Address Bus, RDADD[7:0] .................................................................................................................................................................. 27

Table 6 — Write Queue Switch Operation ...................................................................................................................................................................... 30

Table 7 — Read Queue Switch Operation ..................................................................................................................................................................... 32

Table 8 — Same Queue Switch ..................................................................................................................................................................................... 32

Table 9 — Flag operation boundaries and Timing .......................................................................................................................................................... 45

Table 10 — Packet Mode Valid Byte for x36 bit word configuration ................................................................................................................................. 48

Table 11 — Bus-Matching Set-Up .................................................................................................................................................................................. 52

SEPTEMBER 27, 2004

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592

bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures

Figure 1. Multi-Queue Flow-Control Device Block Diagram .............................................................................................................................................. 6

Figure 2a. AC Test Load ................................................................................................................................................................................................ 19

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 19

Figure 3. Reference Signals .......................................................................................................................................................................................... 22

Figure 4. Device Programming Hierarchy ..................................................................................................................................................................... 24

Figure 5. IDT Standard mode illustrated (Read Port) ..................................................................................................................................................... 25

Figure 6. First Word Fall Through (FWFT) mode illustrated (Read Port) ........................................................................................................................ 25

Figure 7. Write Port Switching Queues Signal Sequence ................................................................................................................................................ 29

Figure 8. Switching Queues Bus Efficiency ..................................................................................................................................................................... 29

Figure 9. Simultaneous Queue Switching ....................................................................................................................................................................... 30

Figure 10. Read Port Switching Queues Signal Sequence ............................................................................................................................................. 31

Figure 11. Switching Queues Bus Efficiency ................................................................................................................................................................... 31

Figure 12. Simultaneous Queue Switching ..................................................................................................................................................................... 32

Figure 13. MARK and Re-Write Sequence .................................................................................................................................................................... 33

Figure 14. MARK and Re-Read Sequence ................................................................................................................................................................... 33

Figure 15. MARKing a Queue in Packet Mode - Write Queue MARK ............................................................................................................................. 34

Figure 16. MARKing a Queue in Packet Mode - Read Queue MARK ............................................................................................................................ 34

Figure 17. UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK ................................................................................................................ 35

Figure 18. UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK ............................................................................................................... 35

Figure 19. MARKing a Queue in FIFO Mode - Write Queue MARK ............................................................................................................................... 37

Figure 20. MARKing a Queue in FIFO Mode - Read Queue MARK .............................................................................................................................. 37

Figure 21. UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK .................................................................................................................. 38

Figure 22. UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK ................................................................................................................. 38

Figure 23. Leaving a MARK active on the Write Port ...................................................................................................................................................... 39

Figure 24. Leaving a MARK active on the Read Port ..................................................................................................................................................... 39

Figure 25. Inactivating a MARK on the Write Port Active ................................................................................................................................................. 40

Figure 26. Inactivating a MARK on the Read Port Active ................................................................................................................................................ 40

Figure 27. 36bit to 36bit word configuration .................................................................................................................................................................... 49

Figure 28. 36bit to 18bit word configuration .................................................................................................................................................................... 49

Figure 29. 36bit to 9bit word configuration ...................................................................................................................................................................... 49

Figure 30. 18bit to 36bit word configuration .................................................................................................................................................................... 50

Figure 31. 18bit to 18bit word configuration .................................................................................................................................................................... 50

Figure 32. 18bit to 9bit word configuration ...................................................................................................................................................................... 50

Figure 33. 9bit to 36bit word configuration ...................................................................................................................................................................... 51

Figure 34. 9bit to 18bit word configuration ...................................................................................................................................................................... 51

Figure 35. 9bit to 9bit word configuration ........................................................................................................................................................................ 51

Figure 36. Bus-Matching Byte Arrangement ................................................................................................................................................................... 53

Figure 37. Master Reset ................................................................................................................................................................................................ 54

Figure 38. Default Programming .................................................................................................................................................................................... 55

Figure 39. Parallel Programming ................................................................................................................................................................................... 56

Figure 40. Queue Programming via Write Address Bus .................................................................................................................................................. 57

Figure 41. Queue Programming via Read Address Bus ................................................................................................................................................. 57

Figure 42. Serial Port Connection for Serial Programming .............................................................................................................................................. 57

Figure 43. Serial Programming (2 Device Expansion) ................................................................................................................................................... 58

Figure 44. Write Queue Select, Write Operation and Full Flag Operation ........................................................................................................................ 59

Figure 45. Write Queue Select, Mark and Rewrite .......................................................................................................................................................... 60

Figure 46. Write Operations in First Word Fall Through mode ....................................................................................................................................... 61

Figure 47. Full Flag Timing in Expansion Configuration .................................................................................................................................................. 62

Figure 48. Read Queue Select, Read Operation (IDT mode) ......................................................................................................................................... 63

Figure 49. Read Queue Select, Read Operation (FWFT mode) ..................................................................................................................................... 64

Figure 50. Read Queue Select, Mark and Reread (IDT mode) ...................................................................................................................................... 65

Figure 51. Output Ready Flag Timing (In FWFT Mode) ................................................................................................................................................. 66

Figure 52. Read Queue Selection with Read Operations (IDT mode) ............................................................................................................................. 67

Figure 53. Read Queue Select, Read Operation and

Timing .................................................................................................................................... 68

Figure 54. Writing in Packet Mode during a Queue change ............................................................................................................................................ 69

SEPTEMBER 27, 2004

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures (Continued)

Figure 55. Reading in Packet Mode during a Queue change ......................................................................................................................................... 70

Figure 56. Writing Demarcation Bits (Packet Mode) ........................................................................................................................................................ 71

Figure 57. Data Output (Receive) Packet Mode of Operation ......................................................................................................................................... 72

Figure 58. Almost Full Flag Timing and Queue Switch .................................................................................................................................................... 73

Figure 59. Almost Full Flag Timing ................................................................................................................................................................................. 73

Figure 60. Almost Empty Flag Timing and Queue Switch (FWFT mode) ......................................................................................................................... 74

Figure 61. Almost Empty Flag Timing ............................................................................................................................................................................. 74

Figure 62.

PAEn/PRn

- Direct Mode - Status Word Selection ......................................................................................................................................... 75

Figure 63.

PAFn

- Direct Mode - Status Word Selection ................................................................................................................................................. 75

Figure 64.

PAEn

- Direct Mode, Flag Operation ............................................................................................................................................................. 76

Figure 65.

PAFn

- Direct Mode, Flag Operation ............................................................................................................................................................. 77

Figure 66.

PAFn

Bus - Polled Mode .............................................................................................................................................................................. 78

Figure 67. Expansion using ID codes ............................................................................................................................................................................ 79

Figure 68. Expansion using

WCS/RCS

......................................................................................................................................................................... 80

Figure 69. Expansion Connection Read Chip Select (RCS) ........................................................................................................................................... 81

Figure 70. Expansion Connection Write Chip Select (WCS) ........................................................................................................................................... 81

Figure 71. Boundary Scan Architecture ......................................................................................................................................................................... 82

Figure 72. TAP Controller State Diagram ....................................................................................................................................................................... 83

Figure 73. Standard JTAG Timing .................................................................................................................................................................................. 86

SEPTEMBER 27, 2004

IDT72P51769L5BB8相似产品对比

	IDT72P51769L5BB8	IDT72P51749L6BB8	IDT72P51759L6BB8	IDT72P51749L5BB8	IDT72P51769L6BB8	IDT72P51759L5BB8
描述	FIFO, 128KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256	FIFO, 32KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256	FIFO, 64KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256	FIFO, 32KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256	FIFO, 128KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256	FIFO, 64KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256	BGA, BGA256,16X16,40	BGA, BGA256,16X16,40	BGA, BGA256,16X16,40	17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256	BGA, BGA256,16X16,40
针数	256	256	256	256	256	256
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
最长访问时间	3.6 ns	3.7 ns	3.7 ns	3.6 ns	3.7 ns	3.6 ns
最大时钟频率 (fCLK)	200 MHz	166 MHz	166 MHz	200 MHz	166 MHz	200 MHz
周期时间	5 ns	6 ns	6 ns	5 ns	6 ns	5 ns
JESD-30 代码	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256
JESD-609代码	e0	e0	e0	e0	e0	e0
长度	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm
内存密度	4718592 bit	1179648 bit	2359296 bit	1179648 bit	4718592 bit	2359296 bit
内存集成电路类型	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO
内存宽度	36	36	36	36	36	36
湿度敏感等级	3	3	3	3	3	3
功能数量	1	1	1	1	1	1
端子数量	256	256	256	256	256	256
字数	131072 words	32768 words	65536 words	32768 words	131072 words	65536 words
字数代码	128000	32000	64000	32000	128000	64000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	128KX36	32KX36	64KX36	32KX36	128KX36	64KX36
可输出	YES	YES	YES	YES	YES	YES
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	BGA	BGA	BGA	BGA	BGA
封装等效代码	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
电源	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	3.5 mm	3.5 mm	3.5 mm	3.5 mm	3.5 mm	3.5 mm
最大待机电流	0.1 A	0.1 A	0.1 A	0.1 A	0.1 A	0.1 A
最大压摆率	0.15 mA	0.15 mA	0.15 mA	0.15 mA	0.15 mA	0.15 mA
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)
端子形式	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm

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“速度与激情“高清监控下双码流回放技术

今天的安防行业，已经进入所谓的大联网时代。许多企业特别是金融机构都已经建立了多级视频监控联网平台。利用遍布全国的网络，金融机构的总部可以随时调用各分支机构的监控录像。然而，在现实应用中，由于带宽的限制，许多企业在进行高清监控的情况下，就无法满足低网速下的远程调用需求。“速度与激情”在中国的安防行业似乎无法兼顾。鉴于这种情况，蓝色星际在国内率先推出了“双码流回放技术”，这种技术可实时导出高、低分辨...[详细]
整合芯片、软件及平台为一体的可穿戴式设计

For healthcare professionals, accurate diagnosis and treatment are crucial for a clear picture of a person's health. However, healthcare professionals often rely on tests at medical facilities, cli...[详细]
速腾聚创：ADAS激光雷达收入下降，但机器人业务扛起大旗

毛利率从去年上半年的13.6%跃升至25.9%，几乎同比翻倍。 8月21日，速腾聚创发布了中期业绩报告，其中毛利率的增长非常亮眼。财报显示，速腾聚创今年上半年收今年第二季度达到了27.7%。其中 ADAS 的毛利率为19.4%，机器人及其他为41.5%，毛利率已经连续第6个季度稳步上升。在电话会上，速腾聚创CEO邱纯潮在业绩会上透露，在L4全球领域的领先企业中，速腾聚创合作的...[详细]
消息称三星正为 2nm 尖端制程导入 Hyper Cell 技术

8 月 22 日消息，韩媒 Nate 当地时间 20 日报道称，三星电子正在向其当下最先进的 2nm 级制程工艺中导入 Hyper Cell 技术，力图以晶体管设计上的更大灵活性提升性能与能效表现，增强工艺在 AI / HPC 芯片代工市场的竞争力。单元 (Cell) 是半导体芯片设计中最基本的单位，而传统的标准单元具有相对固定的高度尺寸和排列方式（即所谓的 6T 库、7.5T 库）。三星的 ...[详细]
超拟人Eva上车，吉利要把汽车变成具身智能生命体！

2025年的汽车行业，正在迎来一场彻底的智能化洗牌。吉利在AI座舱领域想要做出变革：今后吉利的产品线中，将不存在不具备AI能力的传统智能座舱。这是一次“先破后立”。如何做到？吉利给出的答案是“全域AI”，并以此搭建了行业首个五层原生AI座舱架构。在这个架构中，硬件不再只是算力的堆砌，而是与大模型、情感计算、智能体生态深度融合，最终形成一个会思考、能理解、可陪伴的具身智能生命体。...[详细]
单片机开发过程中遇到的关于串口的若干问题

最近做了一个项目，涉及到了串口，本来以为像串口这种经常使用的通讯方式，开发起来应该是很简单的，不说易如反掌，至少也不应该在一个问题上卡壳太久。说到底还是自己经验不足，还得多多学习才是！该项目是使用CubeMX生成的初始化代码，在配置串口的时候我格外小心，该配置的都配置了，但是生成代码后烧到单片机中，却发现串口接收数据出现问题，只能接收到一次数据，后面无论如何都接收不到了。但是我已经在串口初...[详细]
stm32相关笔记——ADC部分

我们在学习一门技术的时候，应该对它的理论部分有所了解，然后才能在实践中进一步加深理解，进而掌握。对于stm32来说，我认为学习的时候应该先仔细阅读相关的参考手册，然后再动手实践，这样才能理解得更加透彻，掌握得更加牢固！今天记录一下我学习stm32的ADC部分的了解。 1.介绍小结：stm32的ADC有18个通道（16个外部通道+2个内部通道），有单次、连续、扫描和间断四种模式，ADC...[详细]
Power Integrations推出太阳能赛车专用参考设计，采用高效率氮化镓芯片

PowiGaN在轻载和满载时均实现95%高效率，满足关键的运行和安全功能需求澳大利亚达尔文及美国加州圣何塞， 2025年8月22日讯 –Power Integrations推出一款专为太阳能赛车量身定制的参考设计套件。与此同时，37支学生队伍已整装待发，将参加于8月24日开始的普利司通世界太阳能挑战赛，穿越澳洲内陆地区。该套件型号为RDK-85SLR，采用了PI™公司一款集成Po...[详细]
燃油车进入智能化拐点，电子电气架构“下放”

过去十年，燃油车的叙事始终是“衰退”与“替代”。在新能源汽车的攻势下，传统车企被迫在电动化的转型赛道上加速。但真正能延长燃油车生命力的，不是新的动力总成，而是智能化架构的“下放”。大众与小鹏联合开发的CEA区域控制电子电气架构，原本是为电动车设计的集中式计算系统，如今正被移植到燃油与混合动力车型。这不是一次简单的技术平移，而是对燃油车定义的重塑：它不再只是依赖机械性能的过渡产品...[详细]
MODBUS转PROFIBUS网关YT-PB-03将仪表接入PROFIBUS的配制方法

工具/原料移通创联MODBUS转PROFIBUS网关YT-PB-03 西门子s7-300 本文主要介绍MODBUS转PROFIBUS网关YT-PB-03将仪表接入PROFIBUS的配制方法。移通创联MODBUS转PROFIBUS网关YT-PB-03广泛应用于变频器、电机启动保护装置、智能高低压电器、电量测量装置、各种变送器、智能现场测量设备及仪表等等,都可以使用该rs485转PROF...[详细]
决定自动驾驶激光雷达感知质量的因素有哪些？

激光雷达（LiDAR）对于自动驾驶汽车来说，就是让自动驾驶汽车“看得见路”的感觉器官，它的工作原理简单描述，就是将激光束打出去、把回波接回来，最后生成三维点云的交通环境。对于车企来说，并不是把“激光雷达”挂在车上，就意味着车辆一定能够能看得清楚、判断得准交通环境，其实激光雷达探测环境的好坏有非常多的影响因素。先从对于激光雷达最重要的，也是直观的“看得多远、看得多细、看得多稳”这三件...[详细]
人工智能功耗问题：挑战、权衡与优化路径

编译自semiengineering 业界越来越关注人工智能的功耗问题，但这个问题并没有简单的解决方案。这需要深入了解应用、半导体和系统层面的软件和硬件架构，以及所有这些的设计和实现方式。每个环节都会影响总功耗和提供的效用。这是最终必须做出的权衡。但首先，必须解决效用问题。电力是否被浪费了？“我们将电力用于有价值的用途，”Ansys（现为新思科技旗下公司）产品营销总监 Marc Swi...[详细]

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