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IDT72P51759L6BB8: 产品描述FIFO, 64KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256; 产品类别存储存储; 文件大小804KB，共87页; 制造商IDT (Integrated Device Technology)

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IDT72P51759L6BB8概述

FIFO, 64KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256

IDT72P51759L6BB8规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	BGA
包装说明	BGA, BGA256,16X16,40
针数	256
Reach Compliance Code	not_compliant
ECCN代码	EAR99
最长访问时间	3.7 ns
最大时钟频率 (fCLK)	166 MHz
周期时间	6 ns
JESD-30 代码	S-PBGA-B256
JESD-609代码	e0
长度	17 mm
内存密度	2359296 bit
内存集成电路类型	OTHER FIFO
内存宽度	36
湿度敏感等级	3
功能数量	1
端子数量	256
字数	65536 words
字数代码	64000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	64KX36
可输出	YES
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装等效代码	BGA256,16X16,40
封装形状	SQUARE
封装形式	GRID ARRAY
并行/串行	PARALLEL
电源	1.8 V
认证状态	Not Qualified
座面最大高度	3.5 mm
最大待机电流	0.1 A
最大压摆率	0.15 mA
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn63Pb37)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
宽度	17 mm
Base Number Matches	1

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1.8V MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 36 BIT WIDE CONFIGURATION

1,179,648 bits

2,359,296 bits

4,718,592 bits

ADVANCE INFORMATION

IDT72P51749

IDT72P51759

IDT72P51769

FEATURES

•

Choose from among the following memory density options:

IDT72P51749



Total Available Memory = 1,179,648 bits

IDT72P51759



Total Available Memory = 2,359,296 bits

IDT72P51769



Total Available Memory = 4,718,592 bits

Configurable from 1 to 128 Queues

Default configuration of 128 or 64 symmetrical queues

Default multi-queue device configurations

– IDT72P51749: 256 x 36 x 128Q

– IDT72P51759: 512 x 36 x 128Q

– IDT72P51769: 1,024 x 36 x 128Q

Default configuration can be augmented via the queue address

bus

Number of queues and individual queue sizes may be

configured at master reset though serial programming

200 MHz High speed operation (5ns cycle time)

3.6ns access time

Independent Read and Write access per queue

•

User Selectable Bus Matching Options:

– x36 in to x36 out

– x18 in to x36 out

– x9 in to x36 out

– x36in to x18out

– x18 in to x18 out

– x9 in to x18 out

– x36in to x9out

– x18 in to x9 out

– x9 in to x9 out

User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL

100% Bus Utilization, Read and Write on every clock cycle

Selectable First Word Fall Through (FWFT) or IDT standard

mode of operation

Ability to operate on packet or word boundaries

Mark and Re-Write operation

Mark and Re-Read operation

Individual, Active queue flags (OR /

EF, IR

FF, PAE, PAF, PR)

8 bit parallel flag status on both read and write ports

Direct or polled operation of flag status bus

Expansion of up to 256 queues

JTAG Functionality (Boundary Scan)

Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

HIGH Performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

FUNCTIONAL BLOCK DIAGRAM

MULTI-QUEUE FLOW-CONTROL DEVICE

WADEN

FSTR

WRADD

WEN

WCLK

WCS

READ CONTROL

Q127

RADEN

ESTR

RDADD

WRITE CONTROL

Q126

REN

RCLK

RCS

Q125

Din

Qout

x36, 18 or x9

DATA IN

x36, x18 or x9

DATA OUT

READ FLAGS

EF/OR

PAE

PAEn

WRITE FLAGS

FF/IR

PAF

PAFn

PRn

6714 drw01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2004

SEPTEMBER 2004

DSC-6714/-

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Table of Contents

Features ........................................................................................................................................................................................................................ 1

Description ................................................................................................................................................................................................................... 5

Pin configuration ......................................................................................................................................................................................................... 7

Detailed description .................................................................................................................................................................................................... 8

Pin descriptions ......................................................................................................................................................................................................... 10

Pin number table ........................................................................................................................................................................................................ 16

Recommended DC operating conditions ................................................................................................................................................................ 17

Absolute maximum ratings ........................................................................................................................................................................................ 17

DC electrical characteristics ..................................................................................................................................................................................... 18

AC electrical characteristics ...................................................................................................................................................................................... 20

Functional description .............................................................................................................................................................................................. 22

Serial Programming .............................................................................................................................................................................................. 23

Default Programming ............................................................................................................................................................................................ 23

Parallel Programming ........................................................................................................................................................................................... 23

Queue description ..................................................................................................................................................................................................... 25

Configuration of the IDT Multi-queue flow-control device ....................................................................................................................................... 25

Standard mode operation ..................................................................................................................................................................................... 26

Read Queue Selection and Read Operation ......................................................................................................................................................... 27

Switching Queues on the Write Port ...................................................................................................................................................................... 29

Switching Queues on the Read Port ..................................................................................................................................................................... 31

Flag description ......................................................................................................................................................................................................... 42

PAFn

Flag Bus Operation .................................................................................................................................................................................... 42

Full Flag Operation ............................................................................................................................................................................................... 42

Empty or Output Ready Flag Operation (EF/OR) .................................................................................................................................................. 42

Almost Full Flag .................................................................................................................................................................................................... 43

Almost Empty Flag ................................................................................................................................................................................................ 43

Packet Ready Flag ............................................................................................................................................................................................... 47

Packet Mode Demarcation bits .............................................................................................................................................................................. 49

JTAG Interface ............................................................................................................................................................................................................ 82

JTAG AC electrical characteristics ............................................................................................................................................................................ 86

Ordering Information ................................................................................................................................................................................................. 87

List of Tables

Table 1 — Device programming mode comparison ........................................................................................................................................................ 22

Table 2 — Setting the queue programming mode during master reset ............................................................................................................................. 22

Table 3 — Mode Configuration ...................................................................................................................................................................................... 25

Table 4 — Write Address Bus, WRADD[7:0] ................................................................................................................................................................... 26

Table 5 — Read Address Bus, RDADD[7:0] .................................................................................................................................................................. 27

Table 6 — Write Queue Switch Operation ...................................................................................................................................................................... 30

Table 7 — Read Queue Switch Operation ..................................................................................................................................................................... 32

Table 8 — Same Queue Switch ..................................................................................................................................................................................... 32

Table 9 — Flag operation boundaries and Timing .......................................................................................................................................................... 45

Table 10 — Packet Mode Valid Byte for x36 bit word configuration ................................................................................................................................. 48

Table 11 — Bus-Matching Set-Up .................................................................................................................................................................................. 52

SEPTEMBER 27, 2004

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592

bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures

Figure 1. Multi-Queue Flow-Control Device Block Diagram .............................................................................................................................................. 6

Figure 2a. AC Test Load ................................................................................................................................................................................................ 19

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 19

Figure 3. Reference Signals .......................................................................................................................................................................................... 22

Figure 4. Device Programming Hierarchy ..................................................................................................................................................................... 24

Figure 5. IDT Standard mode illustrated (Read Port) ..................................................................................................................................................... 25

Figure 6. First Word Fall Through (FWFT) mode illustrated (Read Port) ........................................................................................................................ 25

Figure 7. Write Port Switching Queues Signal Sequence ................................................................................................................................................ 29

Figure 8. Switching Queues Bus Efficiency ..................................................................................................................................................................... 29

Figure 9. Simultaneous Queue Switching ....................................................................................................................................................................... 30

Figure 10. Read Port Switching Queues Signal Sequence ............................................................................................................................................. 31

Figure 11. Switching Queues Bus Efficiency ................................................................................................................................................................... 31

Figure 12. Simultaneous Queue Switching ..................................................................................................................................................................... 32

Figure 13. MARK and Re-Write Sequence .................................................................................................................................................................... 33

Figure 14. MARK and Re-Read Sequence ................................................................................................................................................................... 33

Figure 15. MARKing a Queue in Packet Mode - Write Queue MARK ............................................................................................................................. 34

Figure 16. MARKing a Queue in Packet Mode - Read Queue MARK ............................................................................................................................ 34

Figure 17. UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK ................................................................................................................ 35

Figure 18. UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK ............................................................................................................... 35

Figure 19. MARKing a Queue in FIFO Mode - Write Queue MARK ............................................................................................................................... 37

Figure 20. MARKing a Queue in FIFO Mode - Read Queue MARK .............................................................................................................................. 37

Figure 21. UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK .................................................................................................................. 38

Figure 22. UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK ................................................................................................................. 38

Figure 23. Leaving a MARK active on the Write Port ...................................................................................................................................................... 39

Figure 24. Leaving a MARK active on the Read Port ..................................................................................................................................................... 39

Figure 25. Inactivating a MARK on the Write Port Active ................................................................................................................................................. 40

Figure 26. Inactivating a MARK on the Read Port Active ................................................................................................................................................ 40

Figure 27. 36bit to 36bit word configuration .................................................................................................................................................................... 49

Figure 28. 36bit to 18bit word configuration .................................................................................................................................................................... 49

Figure 29. 36bit to 9bit word configuration ...................................................................................................................................................................... 49

Figure 30. 18bit to 36bit word configuration .................................................................................................................................................................... 50

Figure 31. 18bit to 18bit word configuration .................................................................................................................................................................... 50

Figure 32. 18bit to 9bit word configuration ...................................................................................................................................................................... 50

Figure 33. 9bit to 36bit word configuration ...................................................................................................................................................................... 51

Figure 34. 9bit to 18bit word configuration ...................................................................................................................................................................... 51

Figure 35. 9bit to 9bit word configuration ........................................................................................................................................................................ 51

Figure 36. Bus-Matching Byte Arrangement ................................................................................................................................................................... 53

Figure 37. Master Reset ................................................................................................................................................................................................ 54

Figure 38. Default Programming .................................................................................................................................................................................... 55

Figure 39. Parallel Programming ................................................................................................................................................................................... 56

Figure 40. Queue Programming via Write Address Bus .................................................................................................................................................. 57

Figure 41. Queue Programming via Read Address Bus ................................................................................................................................................. 57

Figure 42. Serial Port Connection for Serial Programming .............................................................................................................................................. 57

Figure 43. Serial Programming (2 Device Expansion) ................................................................................................................................................... 58

Figure 44. Write Queue Select, Write Operation and Full Flag Operation ........................................................................................................................ 59

Figure 45. Write Queue Select, Mark and Rewrite .......................................................................................................................................................... 60

Figure 46. Write Operations in First Word Fall Through mode ....................................................................................................................................... 61

Figure 47. Full Flag Timing in Expansion Configuration .................................................................................................................................................. 62

Figure 48. Read Queue Select, Read Operation (IDT mode) ......................................................................................................................................... 63

Figure 49. Read Queue Select, Read Operation (FWFT mode) ..................................................................................................................................... 64

Figure 50. Read Queue Select, Mark and Reread (IDT mode) ...................................................................................................................................... 65

Figure 51. Output Ready Flag Timing (In FWFT Mode) ................................................................................................................................................. 66

Figure 52. Read Queue Selection with Read Operations (IDT mode) ............................................................................................................................. 67

Figure 53. Read Queue Select, Read Operation and

Timing .................................................................................................................................... 68

Figure 54. Writing in Packet Mode during a Queue change ............................................................................................................................................ 69

SEPTEMBER 27, 2004

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES

(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures (Continued)

Figure 55. Reading in Packet Mode during a Queue change ......................................................................................................................................... 70

Figure 56. Writing Demarcation Bits (Packet Mode) ........................................................................................................................................................ 71

Figure 57. Data Output (Receive) Packet Mode of Operation ......................................................................................................................................... 72

Figure 58. Almost Full Flag Timing and Queue Switch .................................................................................................................................................... 73

Figure 59. Almost Full Flag Timing ................................................................................................................................................................................. 73

Figure 60. Almost Empty Flag Timing and Queue Switch (FWFT mode) ......................................................................................................................... 74

Figure 61. Almost Empty Flag Timing ............................................................................................................................................................................. 74

Figure 62.

PAEn/PRn

- Direct Mode - Status Word Selection ......................................................................................................................................... 75

Figure 63.

PAFn

- Direct Mode - Status Word Selection ................................................................................................................................................. 75

Figure 64.

PAEn

- Direct Mode, Flag Operation ............................................................................................................................................................. 76

Figure 65.

PAFn

- Direct Mode, Flag Operation ............................................................................................................................................................. 77

Figure 66.

PAFn

Bus - Polled Mode .............................................................................................................................................................................. 78

Figure 67. Expansion using ID codes ............................................................................................................................................................................ 79

Figure 68. Expansion using

WCS/RCS

......................................................................................................................................................................... 80

Figure 69. Expansion Connection Read Chip Select (RCS) ........................................................................................................................................... 81

Figure 70. Expansion Connection Write Chip Select (WCS) ........................................................................................................................................... 81

Figure 71. Boundary Scan Architecture ......................................................................................................................................................................... 82

Figure 72. TAP Controller State Diagram ....................................................................................................................................................................... 83

Figure 73. Standard JTAG Timing .................................................................................................................................................................................. 86

SEPTEMBER 27, 2004

IDT72P51759L6BB8相似产品对比

	IDT72P51759L6BB8	IDT72P51749L6BB8	IDT72P51749L5BB8	IDT72P51769L5BB8	IDT72P51769L6BB8	IDT72P51759L5BB8
描述	FIFO, 64KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256	FIFO, 32KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256	FIFO, 32KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256	FIFO, 128KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256	FIFO, 128KX36, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256	FIFO, 64KX36, 3.6ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	BGA, BGA256,16X16,40	BGA, BGA256,16X16,40	BGA, BGA256,16X16,40	17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256	17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256	BGA, BGA256,16X16,40
针数	256	256	256	256	256	256
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
最长访问时间	3.7 ns	3.7 ns	3.6 ns	3.6 ns	3.7 ns	3.6 ns
最大时钟频率 (fCLK)	166 MHz	166 MHz	200 MHz	200 MHz	166 MHz	200 MHz
周期时间	6 ns	6 ns	5 ns	5 ns	6 ns	5 ns
JESD-30 代码	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256
JESD-609代码	e0	e0	e0	e0	e0	e0
长度	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm
内存密度	2359296 bit	1179648 bit	1179648 bit	4718592 bit	4718592 bit	2359296 bit
内存集成电路类型	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO	OTHER FIFO
内存宽度	36	36	36	36	36	36
湿度敏感等级	3	3	3	3	3	3
功能数量	1	1	1	1	1	1
端子数量	256	256	256	256	256	256
字数	65536 words	32768 words	32768 words	131072 words	131072 words	65536 words
字数代码	64000	32000	32000	128000	128000	64000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	64KX36	32KX36	32KX36	128KX36	128KX36	64KX36
可输出	YES	YES	YES	YES	YES	YES
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	BGA	BGA	BGA	BGA	BGA	BGA
封装等效代码	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40	BGA256,16X16,40
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
电源	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	3.5 mm	3.5 mm	3.5 mm	3.5 mm	3.5 mm	3.5 mm
最大待机电流	0.1 A	0.1 A	0.1 A	0.1 A	0.1 A	0.1 A
最大压摆率	0.15 mA	0.15 mA	0.15 mA	0.15 mA	0.15 mA	0.15 mA
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)	Tin/Lead (Sn63Pb37)
端子形式	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	17 mm	17 mm	17 mm	17 mm	17 mm	17 mm

IDT72P51759L6BB8

IDT72P51759L6BB8概述

IDT72P51759L6BB8规格参数

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