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74LVT16500ADGG

产品描述3.3 V 18-bit universal bus transceiver; 3-state
产品类别逻辑    逻辑   
文件大小89KB,共19页
制造商Philips Semiconductors (NXP Semiconductors N.V.)
官网地址https://www.nxp.com/
标准
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74LVT16500ADGG概述

3.3 V 18-bit universal bus transceiver; 3-state

74LVT16500ADGG规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Philips Semiconductors (NXP Semiconductors N.V.)
包装说明TSSOP, TSSOP56,.3,20
Reach Compliance Codeunknow
控制类型INDEPENDENT CONTROL
计数方向BIDIRECTIONAL
JESD-30 代码R-PDSO-G56
逻辑集成电路类型REGISTERED BUS TRANSCEIVER
最大I(ol)0.032 A
位数18
功能数量1
端子数量56
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP56,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源3.3 V
Prop。Delay @ Nom-Su4.2 ns
认证状态Not Qualified
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术BICMOS
温度等级INDUSTRIAL
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
触发器类型NEGATIVE EDGE
Base Number Matches1

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74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
Rev. 03 — 29 May 2006
Product data sheet
1. General description
The 74LVT16500A is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V.
This device is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a
HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
I
18-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and
−32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Negative edge-triggered clock inputs
Latch-up protection:
N
JESD78: exceeds 500 mA
ESD protection:
N
MIL STD 883 Method 3015: exceeds 2000 V
N
CDM JESD22-C101-C exceeds 1000 V

74LVT16500ADGG相似产品对比

74LVT16500ADGG 74LVT16500A 74LVT16500ADL 74LVT16500A_06
描述 3.3 V 18-bit universal bus transceiver; 3-state 3.3 V 18-bit universal bus transceiver; 3-state 3.3 V 18-bit universal bus transceiver; 3-state 3.3 V 18-bit universal bus transceiver; 3-state

 
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