74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
Rev. 03 — 29 May 2006
Product data sheet
1. General description
The 74LVT16500A is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V.
This device is an 18-bit universal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a
HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on
the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When
OEAB is LOW, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The
output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2. Features
I
I
I
I
I
I
I
I
I
I
I
I
I
18-bit bidirectional bus interface
3-state buffers
Output capability: +64 mA and
−32
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Negative edge-triggered clock inputs
Latch-up protection:
N
JESD78: exceeds 500 mA
ESD protection:
N
MIL STD 883 Method 3015: exceeds 2000 V
N
CDM JESD22-C101-C exceeds 1000 V
Philips Semiconductors
74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVT16500ADGG
74LVT16500ADL
−40 °C
to +85
°C
−40 °C
to +85
°C
TSSOP56
SSOP56
Description
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
plastic shrink small outline package; 56 leads;
body width 7.5 mm
Version
SOT364-1
SOT371-1
Type number
4. Functional diagram
1
OEAB
55
CPAB
2
LEAB
27
OEBA
30
CPBA
28
LEBA
30 28 27 55 2
CPBA
LEBA
OEBA
LEAB
CPAB
1
OEAB
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D
4
1
1
1
6D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
001aaf038
001aaf039
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LVT16500A_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 29 May 2006
2 of 19
Philips Semiconductors
74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
Pin description
…continued
Pin
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Description
data input/output A3
data input/output A4
data input/output A5
ground (0 V)
data input/output A6
data input/output A7
data input/output A8
data input/output A9
data input/output A10
data input/output A11
ground (0 V)
data input/output A12
data input/output A13
data input/output A14
supply voltage
data input/output A15
data input/output A16
ground (0 V)
data input/output A17
B-to-A output enable input (active LOW)
B-to-A latch enable input
ground (0 V)
B-to-A clock input (active falling edge)
data input/output B17
ground (0 V)
data input/output B16
data input/output B15
supply voltage
data input/output B14
data input/output B13
data input/output B12
ground (0 V)
data input/output B11
data input/output B10
data input/output B9
data input/output B8
data input/output B7
data input/output B6
ground (0 V)
data input/output B5
data input/output B4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Table 2.
Symbol
A3
A4
A5
GND
A6
A7
A8
A9
A10
A11
GND
A12
A13
A14
V
CC
A15
A16
GND
A17
OEBA
LEBA
GND
CPBA
B17
GND
B16
B15
V
CC
B14
B13
B12
GND
B11
B10
B9
B8
B7
B6
GND
B5
B4
74LVT16500A_3
Product data sheet
Rev. 03 — 29 May 2006
5 of 19
FPGA/CPLD
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