Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
FEATURES
•
3-state non-inverting outputs for bus oriented
applications
•
Wide supply voltage range of 1.2 V to 3.6 V
•
Complies with JEDEC standard no. 8-1A
•
Current drive
±24
mA at 3.0 V
•
Universal bus transceiver with D-type latches and
D-type flip-flops capable of operating in transparent,
latched or clocked mode
•
CMOS low power consumption
•
Direct interface with TTL levels
•
All inputs have bus-hold circuitry
•
Output drive capability 50
Ω
transmission lines at 85
°C
•
Plastic fine-pitch ball grid array package.
DESCRIPTION
The 74ALVCH32501 is a high-performance CMOS
product designed for V
CC
operation at 2.5 V and 3.3 V.
Active bus-hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
I/O
C
PD
PARAMETER
propagation delay A
n
to B
n
; B
n
to A
n
input capacitance
input/output capacitance
power dissipation capacitance per latch
V
I
= GND to V
CC
; note 1
outputs enabled
outputs disabled
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = number of inputs switching;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
CONDITIONS
C
L
= 30 pF; V
CC
= 2.5 V
C
L
= 50 pF; V
CC
= 3.3 V
74ALVCH32501
The 74ALVCH32501 can be used as two 18-bit
transceivers or one 36-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions. Data flow in each direction is
controlled by output enable (OE
AB
and OE
BA
), latch enable
(LE
AB
and LE
BA
), and clock inputs (CP
AB
and CP
BA
).
For A-to-B data flow, the device operates in the
transparent mode when LE
AB
is HIGH. When input LE
AB
is
LOW, the A data is latched if input CP
AB
is held at a HIGH
or LOW level. If input LE
AB
is LOW, the A data is stored in
the latch/flip-flop on the LOW-to-HIGH transition of CP
AB
.
When input OE
AB
is HIGH, the outputs are active. When
input OE
AB
is LOW, the outputs are in the high-impedance
state.
Data flow for B-to-A is similar to that of A-to-B, but uses
inputs OE
BA
, LE
BA
and CP
BA
. The output enables are
complimentary (OE
AB
is active HIGH, and OE
BA
is active
LOW).
To ensure the high-impedance state during power-up or
power-down, pin OE
BA
should be tied to V
CC
through a
pull-up resistor and pin OE
AB
should be tied to GND
through a pull-down resistor. The minimum value of the
resistor is determined by the current-sinking or
current-sourcing capability of the driver.
TYP.
2.8
3.0
4.0
8.0
21
3
ns
ns
UNIT
pF
pF
pF
pF
2004 Oct 13
2
Philips Semiconductors
Product specification
36-bit universal bus transceiver with direction pin;
3-state
FUNCTION TABLE
See notes 1 and 2.
INPUT
nOE
AB
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Notes
1. A-to-B data flow is shown; B-to-A flow is similar but uses nOE
BA
, nLE
BA
and nCP
BA
.
2. H = HIGH voltage level;
h = HIGH voltage level on set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level on set-up time prior to the enable or clock transition;
NC = no change;
X = don’t care;
↑
= LOW-to-HIGH enable or clock transition;
↓
= HIGH-to-LOW enable or clock transition;
Z = high impedance OFF-state.
nLE
AB
H
↓
↓
L
L
L
H
H
↓
↓
L
L
L
L
nCP
AB
X
X
X
H or L
↑
↑
X
X
X
X
↑
↑
H or L
H or L
nA
n
X
h
l
X
h
l
H
L
h
l
h
l
X
X
INTERNAL
REGISTERS
X
H
L
NC
H
L
H
L
H
L
H
L
H
L
OUTPUT
74ALVCH32501
OPERATING MODE
nB
n
Z
Z
Z
Z
Z
Z
H
L
H
L
H
L
H
L
disabled
disabled; latch data
disabled; hold data
disabled; clock data
transparent
latch data and display
clock data and display
hold data and display
2004 Oct 13
3
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