with PLL, based on 64Mx4 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V12C756K4 Series
DESCRIPTION
The HYM72V12C756K4 Series are 128Mx72bits ECC Synchronous DRAM Modules. The modules are composed of thirty six
64Mx4bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II stack package, one 2Kbit EEPROM in 8pin TSSOP package on a
168pin glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the
PCB.
The HYM72V12C756K4 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 1Gbytes memory. The
HYM72V12C756K4 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
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FEATURES
support
PC100MHz
168pin SDRAM Registered DIMM
Serial Presence Detect with EEPROM
1.7” (43.18mm) Height PCB with double sided com-
ponents
Single 3.3±0.3V power supply
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SDRAM internal banks : four banks
Module bank : two physical banks
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4 or 8 or Full page for Sequential Burst
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All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
Data mask function by DQM
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Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HYM72V12C756K4-8
HYM72V12C756K4-P
HYM72V12C756K4-S
Clock
Frequency
125MHz
100MHz
100MHz
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
4 Banks
8K
Normal
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.1/Dec.2002
PC100 SDRAM Registered DIMM
HYM72V12C756K4 Series
PIN DESCRIPTION
PIN
CK0
CKE0
/S0 ~ /S3
BA0, BA1
A0 ~ A12
/RAS, /CAS, /WE
REGE
DQM0 ~ 7
DQ0 ~ DQ63
VCC
V
SS
SCL
SDA
SA0~2
WP
ID1~3
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Register Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
Identification Detect
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
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