based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V16655HCT6 Series
Revision History
Revision
No.
0.1
0.2
0.3
0.4
0.5
0.6
Initial Draft
Pin Assignments #68/152 VCC->VSS
Added Manufacturing Location (Singapore), Changed
Absolute Maximum Ratings PD
Changed SPD Byte93(Work Week) -> Byte94(Wor-
Week), Byte94(Year) -> Byte93(Year)
Changed Burst Read Single Write
Changed Block Diagram
Deleted Preliminary
Aug. 2003
History
Draft Date
Nov. 2001
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Preliminary
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.6 / Aug. 2003
1
16Mx64 bits
PC100 SDRAM Unbuffered DIMM
based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V16655HCT6 Series
DESCRIPTION
The Hynix HYM71V16655HCT6 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 8Mx16bits
CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy
printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM71V16655HCT6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes
memory. The Hynix HYM71V16655HCT6 Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
•
•
•
•
•
•
•
•
PC100MHz support
168pin SDRAM Unbuffered DIMM
Serial Presence Detect with EEPROM
1.25” (31.75mm) Height PCB with double sided components
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
Data mask function by DQM
SDRAM internal banks : four banks
•
•
•
•
•
Module bank : two physical bank
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4 or 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
HYM71V16M655HCT6-8
HYM71V16M655HCT6-P
HYM71V16M655HCT6-S
HYM71V16M655HCLT6-8
HYM71V16M655HCLT6-P
HYM71V16M655HCLT6-S
Clock
Frequency
125MHz
100MHz
100MHz
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
Normal
4 Banks
4K
Low Power
TSOP-II
Gold
125MHz
100MHz
100MHz
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.6 / Aug. 2003
2
PC100 SDRAM Unbuffered DIMM
HYM71V16655HCT6 Series
PIN DESCRIPTION
PIN
CK0~CK3
CKE0, CKE1
/S0 ~ /S3
BA0, BA1
A0 ~ A11
/RAS, /CAS, /WE
DQM0~DQM7
DQ0 ~ DQ63
VCC
V
SS
SCL
SDA
SA0~2
WP
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the ris-
ing edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one of
the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
嵌入式系统
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