NCP5215
Dual Synchronous Buck
Controller for Notebook
Power System
The NCP5215, a high−efficiency and fast−transient−response
dual−channel buck controller, provides a multifunctional power
solution for notebook power system. 180
o
interleaved operation
function between the two channels has capabilities of reducing the
common input capacitor requirement and improving noise immunity.
Adaptive−Voltage−Positioning (AVP) control reduces the
requirement of output filter capacitors. Programmable power−saving
operation ensures high efficiency over entire load range. Input
feedforward voltage−mode control is employed to deal with wide
input voltage range. Transient−Response−Enhancement (TRE)
control for the both channels enables fast transient response.
Features
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MARKING
DIAGRAM
QFN40
MN SUFFIX
CASE 488AR
1 40
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
NCP5215
AWLYYWWG
•
Wide Input Voltage Range: 4.5 V to 24 V
•
Adjustable Output Voltage Range: 0.8 V to 3.0 V
•
Selectable Nominal Fixed Switching Frequency:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
200 kHz, 300 kHz, and 400 kHz
180° Interleaved Operation Function between the Two Channels
Programmable Adaptive−Voltage−Positioning (AVP) Operation
Programmable Transient−Response−Enhancement (TRE) Control
Power Saving Operation under Light Load Condition
Input Feedforward Voltage Mode Control
Resistive or Inductor’s DCR Current Sensing
1% Internal 0.8 V Reference
External Soft−Start Operation
Output Discharge and Soft−Stop
Built−in Gate Drivers
Input Supplies Undervoltage Lockout
Output Overvoltage and Undervoltage Protections
Accurate Overcurrent Protection
Thermal Shutdown Protection
QFN40 Package
This is a Pb−Free Device
PIN CONNECTIONS
34 CS1−/Vo1
40 TRESET1
39 COMP1
36 VDRP1
32 SWN1
35 ILMT1
33 CS1+
38 INV1
FSET
VCC
AGND
VREF
PGOOD1
PGOOD2
EN1
EN2
SS1
31 TG1
30 BST1
29 VCCP1
28 BG1
27 PGND1
26 VIN
25 FPWM#
24 PGND2
23 BG2
22 VCCP2
21 BST2
TG2 20
1
2
3
4
5
6
7
8
9
SS2 10
COMP2 12
INV2 13
FB2 14
VDRP2 15
ILIM2 16
CS2−/Vo2 17
CS2+ 18
TRESET2 11
SWN2 19
Typical Applications
•
Notebook Computers
•
CPU Chipset Power Supplies
ORDERING INFORMATION
Device
NCP5215MNR2G
Package
QFN40
(Pb−Free)
Shipping
2500/T
ape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
37 FB1
NCP5215
(Top View)
©
Semiconductor Components Industries, LLC, 2008
October, 2008
−
Rev. 5
1
Publication Order Number:
NCP5215/D
NCP5215
TRESET1
40
TRE1
5VCC
Vin
CS1+
33
30
DSCH1
FB1
CDIFF1
CCM1
BST1
TG1
SWN1
5VCC
Vo1
CS1+
CS1−
CS1−/Vo1
34
12
Ohm
RAMP GENERATOR
&
PWM LOGIC
1
PWM1
GATE
DRIVER
LSEN1
31
32
Vo1
FB1
37
1
29
28
27
VCCP1
BG1
INV1
VREF
VDRP1
COMP1
38
36
39
VREF
COMP1
SWN1
PGND1
OVP1
CLK
CLK1
VIN
FPWM
Soft Start 1
CDIFF1
Over Current
Detector 1
OC1
THERMAL
SHUTDOWN
VCC
Vin
TSD
FB1
EN1
EN_DRV1
VREF
SS1
EN1
ILIM1
FPWM
5VCC
9
7
35
25
VREF
VCC
FSET
AGND
VREF
2
1
3
4
26
5
6
CLK
CLK2
VIN
FPWM
0.8V
OSC
Digital Counter &
180
o
Phase Shift
OC1
5VCC
PROTECTION
and
CONTROL LOGIC
Vin
NCP5215
DSCH1
PGOOD1
FB2
EN2
OC2
DSCH2
PGOOD2
Vin
VIN
PGOOD1
PGOOD2
TRESET2
OVP2
EN_DRV2
5VCC
Vin
11
TRE2
CS2+
18
CS2−/Vo2
17
12
Ohm
21
BST2
TG2
SWN2
5VCC
Vo2
CS2+
CS2−
DSCH2
FB2
CDIFF2
CCM2
RAMP GENERATOR
&
PWM LOGIC
2
PWM2
20
GATE
DRIVER
LSEN2
19
Vo2
FB2
14
2
22
23
VCCP2
BG2
INV2
VREF
VDRP2
COMP2
13
15
12
VREF
COMP2
SWN2
24
PGND2
SS2
EN2
ILIM2
10
8
16
CDIFF2
Soft Start 2
VREF
Over Current
Detector 2
OC2
Figure 1. Internal Block Diagram and Typical Application
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2
NCP5215
PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
FSET
VCC
AGND
VREF
PGOOD1
PGOOD2
EN1
EN2
SS1
SS2
TRESET2
COMP2
INV2
FB2
VDRP2
ILMT2
CS2− / Vo2
CS2+
SWN2
TG2
BST2
VCCP2
BG2
PGND2
FPWM#
Vin
PGND1
BG1
VCCP1
BST1
TG1
SWN1
CS1+
CS1− / Vo1
ILMT1
VDRP1
FB1
INV1
COMP1
TRESET1
VCC
This pin powers the control section of IC.
Analog Ground
Low noise ground for control section of IC.
Reference Voltage Output
Internal 0.8 V reference output.
Power GOOD 1
Power good indicator of the output voltage of Channel 1. (Open drained)
Power GOOD 2
Power good indicator of the output voltage of Channel 2. (Open drained)
Enable 1
Enable logic input of Channel 1.
Enable 2
Enable logic input of Channel 2.
Soft−Start 1
Soft−starting programmable pin of Channel 1.
Soft Start 2
Soft−starting programmable pin of Channel 2.
Transient Response Enhancement SET 2
Channel 2 Transient−Response−Enhancement (TRE)
programmable pin.
COMP2
Output of the error amplifier of Channel 2.
Inverting Input 2
Error amplifier’s inverting input pin of Channel 2.
Feedback 2
Output voltage feedback of Channel 2.
Voltage Droop 2
Channel 2 voltage droop output to the compensation. This pin is used to program the
adaptive−voltage−position (AVP) function for Channel 2.
Current Limit 2
Current limit programmable pin of Channel 2.
Current Sense 2−
Channel 2 inductor current differential sense inverting input.
Current Sense 2+
Channel 2 inductor current differential sense non−inverting input.
Switch Node 2
Switch node between the top MOSFET and bottom MOSFET of Channel 2.
Top Gate 2
Gate driver output of the top N−Channel MOSFET for Channel 2.
BOOTSTRAP Connection 2
Channel 2 top gate driver input supply, a bootstrap capacitor connection
between SWN2 and this pin.
VCC Power 2
This pin powers the bottom gate driver of Channel 2.
Bottom Gate 2
Gate driver output of the bottom N−Channel MOSFET for Channel 2.
Power Ground 2
Ground reference and high−current return path for the bottom gate driver of Channel 2.
Forced PWM
Forced PWM enable logic input. Low to enable forced PWM mode and disable power−saving
mode for both channels.
Vin
Input voltage monitor input.
Power Ground 1
Ground reference and high−current return path for the bottom gate driver of Channel 1.
Bottom Gate 1
Gate driver output of the bottom N−Channel MOSFET for Channel 1.
VCC Power 1
This pin powers the bottom gate driver of Channel 1.
BOOTSTRAP Connection 1
Channel 1 top gate driver input supply, a bootstrap capacitor connection
between SWN1 and this pin.
Top Gate 1
Gate driver output of the top N−Channel MOSFET for Channel 1.
Switch Node 1
Switch node between the top MOSFET and bottom MOSFET of Channel 1.
Current Sense 1+
Channel 1 inductor current differential sense non−inverting input.
Current Sense 1−
Channel 1 inductor current differential sense inverting input.
Current Limit 1
Current limit programmable pin of Channel 1.
Voltage Droop 1
Channel 1 voltage droop output to the compensation. This pin is used to program the
Adaptive−Voltage−Position (AVP) function for Channel 1.
Feedback 1
Output voltage feedback of Channel 1.
Inverting Input 1
Error amplifier’s inverting input pin of Channel 1.
COMP1
Output of the error amplifier of Channel 1.
Transient Response Enhancement SET 1
Channel 1 Transient−Response−Enhancement (TRE)
program pin.
Description
Frequency SET
Programmable pin of switching frequency for two channels.
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3
NCP5215
MAXIMUM RATINGS
Rating
Power Supply Voltages to AGND
High−Side Gate Driver Supplies: BST1 to SWN1, BST2 to SWN2
High−Side FET Gate Driver Voltages: TG1 to SWN1, TG2 to SWN2
Symbol
V
CC
, V
CCP1
,
V
CCP2
V
BST1
−
V
SWN1
,
V
BST2
−
V
SWN2
,
V
TG1
−
V
SWN1
,
V
TG2
−
V
SWN2
,
V
in
V
SWN1
, V
SWN2
V
GND
R
qJA
T
J
T
A
T
stg
MSL
Value
−0.3,
6.0
−0.3,
6.0
Unit
V
V
Input Voltage Sense Inputs to AGND
Switch Nodes
PGND1, PGND2 to AGND
Thermal Characteristics
Thermal Resistance, Junction−to−Air (Pad soldered to PCB)
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
Moisture Sensitivity Level
−0.3,
27
−4.0
(<100 ns),
−0.3
(dc), 32
−0.3,
0.3
36
−40
to +150
−40
to +85
−55
to +150
1
V
V
V
°C/W
°C
°C
°C
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains ESD protection and exceeds the following tests:
Human Body Model (HBM)
≤2.0kV
per JEDEC standard: JESD22−A114.
Machine Model (MM) =≤200V per JEDEC standard: JESD22−A115, except Pin 17 and Pin 34, which are
≤150V.
2. Latchup Current Maximum Rating:
≤150mA
per JEDEC standard: JESD78.
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NCP5215
ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0 V, V
IN
= 12 V, F
SET
= 5.0 V, Fsw = 300 kHz, T
A
=
−40°C
to 85°C, unless otherwise
Characteristic
SUPPLY VOLTAGE
Input Voltage
V
CC
Operating Voltage
V
CCP1
Operating Voltage
V
CCP2
Operating Voltage
SUPPLY CURRENT
V
CC
Quiescent Supply Current in Normal
Operation
V
CC
Quiescent Supply Current in
Power−Saving Operation
V
CC
Shutdown Current
V
CCP
Quiescent Supply Current in Normal
Operation
V
CCP
Shutdown Current
BST Quiescent Supply Current in Normal
Operation
BST Shutdown Current
VOLTAGE−MONITOR
V
CC
Start Threshold
V
CC
UVLO Hysteresis
Power Good Higher Threshold
Power Good Lower Threshold
Output Overvoltage Trip Threshold
Overvoltage Fault Propagation Delay
Output Undervoltage Trip Threshold
Output Undervoltage Protection Blanking
Time
VREF OUTPUT
Reference Voltage
Reference Load Regulation
Sinking Current
CURRENT LIMIT
Current Limit Threshold
ILIM Setting Range
3. Guaranteed by design, not tested in production.
V
((CS+)−(CS−))
Range
ILIM
V
ILIM
= 0.4 V
(Note 3)
72
−
80
−
88
0.8
mV
V
V
ref
DV
ref
Isink_VREF
T
A
= 25°C
T
A
=
−40
to 85°C
Ivref = 0 to 100
mA
Vref rises 10%
0.796
0.792
−
20
0.8
−
−
−
0.804
0.808
4.0
−
V
mV
mA
VCC
UV+
VCC
hys
VPGH
VPGL
FBOVPth
−
FBUVPth
UVPT
blk
V
CC
and V
CCP
are connected to
the same voltage source
−
With Respect to Error Comparator
Threshold of 0.8 V
With Respect to Error Comparator
Threshold of 0.8 V
With respect to Error Comparator
Threshold of 0.8 V
FB forced 2% above trip threshold
With respect to Error Comparator
Threshold of 0.8 V
(Note 3)
4.05
200
−
−
113
−
63
−
4.25
275
112
88
117
1.5
68
16/fsw
4.48
400
−
−
121
−
73
−
V
mV
%
%
%
ms
%
s
I
VCC_N
VEN1 = VEN2 = 5.0 V,
VFPWM# = 0 V TG1, BG1, TG2,
and BG2 are open
VEN1 = VEN2 = 5.0 V,
VFPWM# = 5.0 V TG1, BG1,
TG2, and BG2 are open
VEN1 = VEN2 = 0 V
VEN1 = VEN2 = 5.0 V,
VFPWM# = 0 V TG1, BG1, TG2,
and BG2 are open
VEN1 = VEN2 = 0 V
VEN1 = VEN2 = 5.0 V,
VFPWM# = 0 V TG1, BG1, TG2,
and BG2 are open
VEN1 = VEN2 = 0 V
−
3.0
6.0
mA
Vin
V
CC
V
CCP1
V
CCP2
−
−
−
−
4.5
4.5
4.5
4.5
−
5.0
5.0
5.0
24
5.5
5.5
5.5
V
V
V
V
Symbol
Test Conditions
Min
Typ
Max
Unit
noted.)
I
VCC_PS
−
3.0
6.0
mA
I
VCC_SD
I
VCCP1_N
,
I
VCCP2_N
I
VCCP1_SD
,
I
VCCP2_SD
I
BST1_N
, I
BST2_N
−
−
−
1.2
10
2.0
mA
mA
−
−
−
1.0
10
2.0
mA
mA
I
BST1_SD
,
I
BST2_SD
−
−
5.0
mA
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