4-BIT D LATCH
The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as tem-
porary storage for binary information between processing units and input /out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
The SN54 / 74LS75 features complementary Q and Q output from a 4-bit
latch and is available in the 16-pin packages. For higher component density
applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
CONNECTION DIAGRAMS DIP
(TOP VIEW)
Q0
16
Q1
15
Q1
14
E0–1 GND
13
12
Q2
11
Q2
10
Q3
9
16
SN54/74LS75
SN54/74LS77
4-BIT D LATCH
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
1
SN54 / 74LS75
N SUFFIX
PLASTIC
CASE 648-08
1
1
Q0
Q0
14
2
D0
Q1
13
3
D1
4
5
E2–3 VCC
NC
10
6
D2
Q2
9
7
D3
Q3
8
8
Q3
16
E0–1 GND
12
11
16
1
D SUFFIX
SOIC
CASE 751B-03
SN54 / 74LS77
J SUFFIX
CERAMIC
CASE 632-08
14
1
1
D0
PIN NAMES
2
D1
3
E2–3
4
VCC
5
D2
6
D3
7
NC
LOADING
(Note a)
HIGH
LOW
0.25 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
D1–D4
E0–1
E2–3
Q1–Q4
Q1–Q4
Data Inputs
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
0.5 U.L.
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
14
1
N SUFFIX
PLASTIC
CASE 646-06
NOTES:
a) 1 Unit Load (U.L.) = 40
µA
HIGH.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
14
1
D SUFFIX
SOIC
CASE 751A-02
TRUTH TABLE
(Each latch)
ORDERING INFORMATION
tn
D
H
L
tn + 1
Q
H
L
NOTES:
tn = bit time before enable
negative-going transition
tn+1 = bit time after enable
negative-going transition
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
FAST AND LS TTL DATA
5-1
SN54/74LS75
LOGIC SYMBOLS
SN54/74LS75
2
D0
E0–1
E2–3
3
D1
6
D2
7
D3
VCC = PIN 5
GND = PIN 12
12
3
1
SN54/74LS77
2
D1
5
D2
6
D3
VCC = PIN 4
GND = PIN 11
NC = PIN 7, 10
13
4
D0
E0–1
E2–3
Q0
14
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
16 1 15 14 10 11 9
8
Q1
13
Q2
9
Q3
8
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
S b l
VIH
VIL
VIK
VOH
Parameter
P
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
D Input
E Input
IIH
Input HIGH Current
D Input
E Input
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
D Input
E Input
– 20
0.1
0.4
– 0.4
–1.6
–100
12
mA
VCC = MAX, VIN = 7.0 V
0.35
0.5
20
80
V
µA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
U i
V
Test C di i
T
Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
p
g
All Inputs
VCC = MIN, IIN = – 18 mA
,
,
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
IIL
IOS
ICC
mA
mA
mA
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
S b l
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Parameter
P
Propagation Delay, Data to Q
Propagation Delay, Data to Q
Propagation Delay, Enable to Q
Propagation Delay, Enable to Q
Min
Typ
15
9.0
12
7.0
15
14
16
7.0
Max
27
17
20
15
27
25
30
15
Unit
U i
ns
ns
ns
ns
Test C di i
T
Conditions
VCC = 5.0 V
50
CL = 15 pF
FAST AND LS TTL DATA
5-2
SN54/74LS77
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
S b l
VIH
VIL
VIK
VOH
Parameter
P
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
D Input
E Input
IIH
Input HIGH Current
D Input
E Input
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
D Input
E Input
– 20
0.1
0.4
– 0.4
–1.6
–100
13
mA
VCC = MAX, VIN = 7.0 V
0.35
0.5
20
80
V
µA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
U i
V
Test C di i
T
Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
p
g
All Inputs
VCC = MIN, IIN = – 18 mA
,
,
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
IIL
IOS
ICC
mA
mA
mA
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
S b l
tPLH
tPHL
tPLH
tPHL
Parameter
P
Propagation Delay, Data to Q
Propagation Delay, Enable to Q
Min
Typ
11
9.0
10
10
Max
19
17
18
18
Unit
U i
ns
ns
VCC = 5.0 V
CL = 15 pF
Test C di i
T
Conditions
FAST AND LS TTL DATA
5-3
SN54/74LS75
D
SN54/74LS77
LOGIC DIAGRAM
DATA
ENABLE
TO OTHER LATCH
Q (SN54/74LS75 ONLY)
Q
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
AC SETUP REQUIREMENTS
(TA = 25°C, VCC = 5.0 V)
Limits
Symbol
S b l
tW
ts
th
Parameter
P
Enable Pulse Width High
Setup Time
Hold Time
Min
20
20
0
Typ
Max
Unit
U i
ns
ns
ns
VCC = 5.0 V
50
Test C di i
T
Conditions
AC WAVEFORMS
D
1.3 V
ts
E
1.3 V
tPLH
Q
tPLH
1.3 V
tPHL
tPHL
Q
tPHL
tPHL
1.3 V
tPLH
tPLH
1.3 V
1.3 V
1.3 V
1.3 V
th
1.3 V
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the
clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be
maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may
be released prior to the clock transition from HIGH-to-LOW and still be recognized.
FAST AND LS TTL DATA
5-4
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