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LF411JAN Low Offset, Low Drift JFET Input Operational Amplifier
October 2005
LF411JAN
Low Offset, Low Drift JFET Input Operational Amplifier
General Description
This device is a low cost, high speed, JFET input operational
amplifier with very low input offset voltage and guaranteed
input offset voltage drift. It requires low supply current yet
maintains a large gain bandwidth product and fast slew rate.
In addition, well matched high voltage JFET input devices
provide very low input bias and offset currents. The LF411 is
pin compatible with the standard LM741 allowing designers
to immediately upgrade the overall performance of existing
designs.
This amplifier may be used in applications such as high
speed integrators, fast D/A converters, sample and hold
circuits and many other circuits requiring low input offset
voltage and drift, low input bias current, high input imped-
ance, high slew rate and wide bandwidth.
Features
n
n
n
n
n
n
n
n
n
Internally trimmed offset voltage:
0.5 mV(Typ)
Input offset voltage drift:
30 µV/˚C
Low input bias current:
50 pA
Low input noise current:
0.01 pA/
√
Hz
Wide gain bandwidth:
3 MHz Typ.
High slew rate:
7V/µs (min.)
Low supply current:
1.8 mA
High input impedance:
10
12
Ω
Low total harmonic distortion: A
V
= 10, R
L
= 10KΩ,
<
0.02%
V
O
= 20V
P-P
, BW = 20Hz - 20KHz
n
Low 1/f noise corner:
50 Hz
n
Fast settling time to 0.01%:
1.5 µs
Ordering Information
NS Part Number
JL411BPA
JAN Part Number
JM38510/11904BPA
NS Package Number
J08A
Package Description
8LD CERDIP
Connection Diagram
8LD Ceramic Dual-in Line Package
Typical Connection
20152407
Top View
See NS Package Number J08A
20152401
BI-FET II
™
is a trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation
DS201524
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LF411JAN
Simplified Schematic
20152406
Detailed Schematic
20152434
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2
LF411JAN
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Differential Input Voltage
Input Voltage Range (Note 4)
Output Short Circuit Duration
Power Dissipation (Note 2), (Note 3)
T
Jmax
Thermal Resistance
θ
JA
Still Air
400LF/Min Air Flow
θ
JC
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Package Weight (Typical)
ESD Tolerance (Note 5)
162˚C/W
65˚C/W
20˚C/W
−55˚C
≤
T
A
≤
125˚C
−65˚C
≤
T
A
≤
150˚C
300˚C
TBD
750V
±
18V
±
30V
±
15V
Continuous
400mW
175˚C
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
1
2
3
4
5
6
7
8A
8B
9
10
11
12
13
14
Description
Static tests at
Static tests at
Static tests at
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
Temp ˚C
25
125
-55
25
125
-55
25
125
-55
25
125
-55
25
125
-55
3
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LF411JAN
Electrical Characteristics
DC Parameters
The following conditions apply to all the following parameters, unless otherwise specified.
DC: V
CC
=
±
15V, V
CM
= 0V
Symbol
V
IO
Parameter
Input Offset Voltage
Conditions
+V
CC
= 26V, -V
CC
= -4V,
V
CM
= -11V
+V
CC
= 4V, -V
CC
= -26V,
V
CM
= 11V
Notes
Min
-5.0
-7.0
-5.0
-7.0
-5.0
-7.0
Max
5.0
7.0
5.0
7.0
5.0
7.0
5.0
7.0
0.2
50
0.2
50
1.2
70
0.1
20
Unit
mV
mV
mV
mV
mV
mV
mV
mV
nA
nA
nA
nA
nA
nA
nA
nA
dB
dB
dB
mV
-8.0
t
≤
25mS
t
≤
25mS
-80
80
3.5
4.0
∆V
IO
/
∆T
+V
OP
-V
OP
+A
VS
-A
VS
A
VS
Input Offset Voltage
Output Voltage Swing
Output Voltage Swing
Open Loop Voltage Gain
Open Loop Voltage Gain
Open Loop Voltage Gain
25˚C
≤
T
A
≤
+125˚C
-55˚C
≤
T
A
≤
25˚C
R
L
= 10KΩ
R
L
= 2KΩ
R
L
= 10KΩ
R
L
= 2KΩ
R
L
= 2KΩ,
V
O
= 0 to 10V
R
L
= 2KΩ,
V
O
= 0 to -10V
R
L
= 10KΩ, V
O
=
±
2V,
±
V
CC
=
±
5V
(Note 7)
(Note 7)
(Note 7)
(Note 7)
(Note 7)
50
25
50
25
20
(Note 6)
(Note 6)
-30
-30
12
10
-12
-10
30
30
mV
mA
mA
mA
mA
µV/˚C
µV/˚C
V
V
V
V
K
K
K
K
K
Sub-
groups
1
2, 3
1
2, 3
1
2, 3
1
2, 3
1
2
1
2
1
2
1
2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
3
2
3
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4
5, 6
4
5, 6
4, 5, 6
±
V
CC
=
±
5V
±
I
IB
Input Bias Current
+V
CC
= 26V, -V
CC
= -4V,
V
CM
= -11V, t
≤
25mS
t
≤
25mS
+V
CC
= 4V, -V
CC
= -26V,
V
CM
= 11V, t
≤
25mS
I
IO
+PSRR
-PSRR
CMR
V
IO Adj
+
V
IO Adj
-
I
OS
+
I
OS
-
I
CC
Input Offset Current
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Input Voltage Common Mode
Rejection
Adjustment for Input Offset
Voltage
Adjustment for Input Offset
Voltage
Output Short Circuit Current
Output Short Circuit Current
Supply Current
t
≤
25mS
+V
CC
= 10V to 20V,
-V
CC
= -15V
+V
CC
= 15V,
-V
CC
= -10V to -20V
V
CM
= -11V to +11V
-5.0
-7.0
-0.4
-10
-0.2
-10
-0.2
-10
-0.1
-20
80
80
80
8.0
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