MT34013
EIGHT CHANNEL ARINC DECODER
•
8/16 bit parallel interface
•
3 channels programmable to HIGH/LOW
speed data
•
Single 5V supply with low power
consumption
<
50mW
•
Full MIL operating range
•
Programmable test I/P to all channels
•
Built in parity and word length error
detection
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
1
MT34013
MAXIMUM RATINGS
(Above which the useful life may be impaired)
Storage Temperature
Temperature (Ambient) under Bias
Supply Voltage VDD
DC Input Voltage
Output Current (Single O/P)
Output Current (Total O/P)
ELECTRICAL CHARACTERISTICS over operating range
PARAMETER
IOH
IOL
VIH
VIL
IIL
IOZ
CI
CI/O
ICC
DESCRIPTION
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input Load Current
Output Leakage Current
Input Capacitance
I/O Capacitance
Supply Current
- 65ºC to +150ºC
- 55ºC to +125ºC
-0.3V to + 7V
-0.3 to VDD +0.3V
10mA
20mA
TEST CONDITIONS
VOH=2.8V
VDD= 4.5V
VOL=0.4V
MIN
1.0
3.2
2.4
-0.3
-40
TYP
MAX
UNITS
mA
mA
Volts
Volts
uA
uA
pF
pF
mA
VSS
0.4V
<
VO
<
VCC Output Disabled
Test Frequency = 1.0 MHZ
VCC = MAX. All inputs
HIGH, All inputs open
.
2
7
VCC
0.8
40
40
2.6
9
10
ARINC 429 SERIAL INPUT INTERFACE
Interfaces are provided for 8 independent Arinc 429 serial input channels with sufficient digital storage to guarantee
no data is lost provided all 8 channels can be accessed within 230
µ
S.
Channels 0,1 & 2 can be programmed for either high or low speed operation. Channels 3 to 7 are configured for
interfacing to low speed Arinc buses only.
Digital Filtering is incorporated on each decoder input port to prevent word corruption due to noise spikes. (The
duration of reject noise spikes is a function of the basic clock period).
Arinc have suggested that the number of labels available to the user can be increased by either using SDI bits 9 and 10
as extra label bits or by using port identification. Both of these techniques have been accommodated in the design.
DATA DETECTION AND WORD TESTS
Each channel is provided with a 32 bit shift register to hold one complete word. The three channels which are
selectable for either high or low speed operation are additionally provided with a 32 bit buffer register.
Each channel contains hardware to test the following parameters:-
(1)
(2)
(3)
Word length of 32 bits.
Parity:- odd on good words.
Gap:- the presence of a 33rd bit is checked for and the output processing is achieved during the remaining
gap for a valid word.
Interconnection fault (both I/P’s high).
(4)
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
2
MT34013
Prioritised error information for each channel is latched into a 3 bit register with the format indicated in Table 1 and
made available at the user output port.
Channel servicing is carried out on a rotating priority basis, where the last channel serviced is given the lowest
priority, in order to allow full access for each channel.
A facility is provided on the decoder chip to enable individual channels to be tested, which consists of a multi-plexer
on the input to each channel to allow test messages (generated external to the chip) to be injected.
TABLE 1
Prioritorised coded error data.
Bit position relative to first output word see fig.2.
15
1
1
1
1
0
0
0
0
14
1
1
0
0
1
1
0
0
13
1
0
1
0
1
0
1
0
)
)
Unused
Interconnection fault (highest priority)
Channel overrun (causes corruption of following word in that channel.
Word length error (number of bits not equal to 32).
Parity error (word received with even parity).
Service overrun (not all words or bytes accessed) - lowest priority.
Good word.
USER INTERFACE
Arinc 429 data is read from the decoder chip via an 8 or 16 bit parallel data bus.
Fig 2 illustrates the formatting of the output data relative to the generalised Arinc 429 word format.
Control of the chip is achieved via a four bit control port which provides the user with the facilities outlined in Table
2. The control word is strobed into the chip using the leading edge of the NOT CSTR input providing the required set
up and hold times are met.
N.B. NOT CSTR must be high before NOT RESET is removed.
DATA READY signifies to the user that a word is available and can be accessed by pulling NOT CHIP ENABLE low
and strobing the NOT OUTPUT SELECT line as illustrated in fig .3.
NOT RESET provides the user with a simple means of asynchronously inhibiting the chip. Activating NOT RESET
disables the output buffers and clears DATA READY asynchronously. The internal counters are cleared by holding
NOT RESET low for 2 clock periods. Default options are selected which can be overwritten using the control input
port. The default options are shown below and are selected by pulsing RESET low or by selecting software reset (see
table 2).
•
•
•
Channel sequencer set to channel 0 for highest priority.
All channels are set for low speed operation.
All channels are set for normal reception with no end around test mode.
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
3
MT34013
NOT CSTR and NOT OS must be high during reset but may go low immediately NOT RESET is removed.
NOT CSTR, LOW min = HIGH min = 1.5T for correct operation CO-3, SET UP TIME = 0, HOLD TIME = 2T min
after NOT CSTR goes low.
NOT CSTR is synchronised by
Ø
IN to give a 0.5T interval strobe pulse. This pulse disables the state decoder O/P’s
allowing 0.5T settling time for the new state to be established before re-enabling the O/P’s. This ensures that data
I/P’s cannot be internally shorted together when changing from test on one channel to another.
*T =
1
/
f
= 1 clock cycle time of
Ø
IN.
A single phase clock must be provided by the user with a frequency in the range of 1.25 - 2.0 MH
Z
. The chip will
accommodate all the selectable channel speed options available with the clock at any frequency between these limits.
A 3 bit binary code is allocated in the first word of output data to signify which channel has received a message and is
being accessed.
The positioning of the code is shown in fig 2 and has the form shown below:-
1st output word bit number
12
0
0
0
0
1
1
1
1
11
0
0
1
1
0
0
1
1
10
0
1
0
1
0
1
0
1
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
FIG. 1
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
4
MT34013
TABLE 2
CONTROL WORD CODES
Control bit number
C3
0
0
0
0
0
C2
0
0
0
0
1
C1
0
0
1
1
0
C0
0
1
0
1
0 (
(
1 (
0 (
1
0
1
0
1
0
1
0
1
Channels 0 to 7 low speed
Channel 0 high speed, channels 1 to 7 low speed
Channel 1 high speed, channels 0 and 2 to 7 low speed
Channels 0 and 1 high speed, channels 2 to 7 low speed
Channels 0,1 & 2 high speed
Channels 3 to 7 low speed
Unused
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
Software reset
Test Channel 0
Test Channel 1
Test Channel 2
Test Channel 3
Test Channel 4
Test Channel 5
Test Channel 6
Test Channel 7
Notes
(1)
Software reset causes the same action as pulling the RESET line low but once latched into the control register
the chip is held in a quiescent mode. Exit from this mode is achieved by latching in the required channel
speed option.
Exit from the test mode requires restarting the required speed options (i.e. codes 0 to 4) or loading an unused
control mode.
The action of testing a channel does not alter the speed at which is set, also changing between test (i.e. test 1
to test 2) has no effect on channel speed settings.
(2)
(3)
VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS
5
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