CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
2.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
3. For
JC
, the “case temp” location is taken at the package top center.
Static Electrical Specifications
At T
A
= -40°C to +85°C, V
DD
= V
BATT
= 5V ±5%, Unless Otherwise Specified.
CDP68HC68T1
PARAMETER
Quiescent Device Current
Output Voltage High Level
Output Voltage Low Level
Output Voltage High Level
Output Voltage Low Level
Input Leakage Current
Three-State Output Leakage Current
Operating Current (Note 5)
(I
D
+ I
B
) V
DD
= V
B
= 5V
Crystal Operation
SYMBOL
I
DD
V
OH
V
OL
V
OH
V
OL
I
IN
I
OUT
32kHz
1MHz
2MHz
4MHz
XTAL IN Clock (Squarewave) (Note 5)
(I
D
+ I
B
) V
DD
= V
S
= 5V
32kHz
1MHz
2MHz
4MHz
Standby Current (Note 5)
V
S
= 3V
Crystal Operation
I
B
32kHz
1MHz
2MHz
4MHz
I
OH
= -1.6mA, V
DD
= 4.5V
I
OL
= 1.6mA, V
DD
= 4.5V
I
OH
10µA,
V
DD
= 4.5V
I
OL
10µA,
V
DD
= 4.5V
TEST CONDITIONS
MIN
-
3.7
-
TYP
(Note 4)
1
-
-
-
-
-
-
0.08
0.5
0.7
1
0.02
0.1
0.2
0.4
20
200
300
500
MAX
10
-
0.4
-
0.1
±1
±10
-
-
-
-
0.024
0.12
0.24
0.5
-
-
-
-
UNITS
µA
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
4.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FN1547 Rev 9.00
Decemember 8, 2015
Page 3 of 24
CDP68HC68T1
Static Electrical Specifications
At T
A
= -40°C to +85°C, V
DD
= V
BATT
= 5V ±5%, Unless Otherwise Specified.
(Continued)
CDP68HC68T1
PARAMETER
Operating Current (Note 5)
V
DD
= 5V, V
B
= 3V
Crystal Operation
SYMBOL
TEST CONDITIONS
MIN
TYP
(Note 4)
I
D
32kHz
1MHz
2MHz
4MHz
Standby Current (Note 5)
V
B
= 2.2V
Crystal Operation
Input Capacitance
Maximum Rise and Fall Times
(Except XTAL Input and POR Pin 10)
Input Voltage (Line Input Pin Only, Power Sense
Mode)
V
SYS
> V
B
V
T
(For V
B
Not Internally Connected to V
DD
)
Power-On Reset (POR) Pulse Width
NOTES:
4. Typical values are for T
A
= +25°C and nominal V
DD
.
5. Clock out (Pin 1) disabled, outputs open circuited. No serial access cycles.
本帖最后由 白丁 于 2015-12-23 22:58 编辑
ge-newline">Before going into a detailed analysis of the two interfaces it will be helpful to establish acommon understanding of the ele ......