DATASHEET
CDP68HC68T1
CMOS Serial Real-Time Clock With RAM and Power Sense/Control
The CDP68HC68T1 Real-Time Clock provides a
time/calendar function, a 32 byte static RAM, and a 3 wire
Serial Peripheral Interface (SPI Bus). The primary function of
the clock is to divide down a frequency input that can be
supplied by the on-board oscillator in conjunction with an
external crystal or by an external clock source. The internal
oscillator can operate with a 32kHz, 1MHz, 2MHz, or 4MHz
crystal. An external clock source with a 32kHz, 1MHz, 2MHz,
4MHz, 50Hz or 60Hz frequency can be used to drive the
CDP68HC68T1. The time registers hold seconds, minutes,
and hours, while the calendar registers hold day-of-week,
date, month, and year information. The data is stored in BCD
format. In addition, 12 or 24 hour operation can be selected.
In 12 hour mode, an AM/PM indicator is provided. The T1
has a programmable output which can provide one of seven
outputs for use elsewhere in the system.
Computer handshaking is controlled with a “wired-OR” interrupt
output. The interrupt can be programmed to provide a signal as
the result of:
1. An alarm programmed to occur at a predetermined
combination of seconds, minutes, and hours.
2. One of 15 periodic interrupts ranging from sub-second to
once per day frequency.
3. A power fail detect. The PSE output and the V
SYS
input are
used for external power control. The CPUR output is
available to reset the processor under power-down
conditions. CPUR is enabled under software control and
can also be activated via the CDP68HC68T1’s watchdog. If
enabled, the watchdog requires a periodic toggle of the CE
pin without a serial transfer.
FN1547
Rev 9.00
Decemember 8, 2015
Features
• SPI (Serial Peripheral Interface)
• Full Clock Features
- Seconds, Minutes, Hours (12/24, AM/PM), Day of
Week, Date, Month, Year (0 to 99), Automatic Leap Year
• 32 Wordx8-Bit RAM
• Seconds, Minutes, Hours Alarm
• Automatic Power Loss Detection
• Low Minimum Standby (Timekeeping) Voltage . . . . . 2.2V
• Selectable Crystal or 50/60Hz Line Input
• Buffered Clock Output
• Battery Input Pin that Powers Oscillator and also
Connects to V
DD
Pin When Power Fails
• Three Independent Interrupt Modes
- Alarm
- Periodic
- Power-Down Sense
• Pb-Free Available (RoHS Compliant)
Pinouts
CDP68HC68T1
(16 LD PDIP, SOIC)
TOP VIEW
CLKOUT
CPUR
INT
SCK
MOSI
MISO
CE
V
SS
1
2
3
4
5
6
7
8
16 V
DD
15 XTAL OUT
14 XTAL IN
13 V
BATT
12 V
SYS
11 LINE
10 POR
9
PSE
CLK OUT
CPUR
INT
NC
SCK
MOSI
MISO
CE
V
SS
1
2
3
4
5
6
7
8
9
CDP68HC68T1
(20 LD SOIC)
TOP VIEW
20 VDD
19 XTAL OUT
18 XTAL IN
17 NC
16 V
BATT
15 V
SYS
14 NC
13 NC
12 LINE
11 POR
PSE 10
FN1547 Rev 9.00
Decemember 8, 2015
Page 1 of 24
CDP68HC68T1
Ordering Information
PART NUMBER
CDP68HC68T1E
(No longer available, recommended
replacement: CDP68HC68T1EZ)
CDP68HC68T1EZ (Note)
CDP68HC68T1M*
(No longer available, recommended
replacement: CDP68HC68T1MZ)
CDP68HC68T1MZ* (Note)
CDP68HC68T1M2*
(No longer available, recommended
replacement: CDP68HC68T1M2Z)
CDP68HC68T1M2Z* (Note)
PART MARKING
CDP68HC68T1E
TEMP RANGE (°C)
-40 to +85
PACKAGE
16 Ld PDIP
PKG DWG. #
E16.3
CDP68HC68T1EZ
68HC68T1M
-40 to +85
-40 to +85
16 Ld PDIP**
(Pb-free)
20 Ld SOIC
Tape and Reel
20 Ld SOIC (Pb-free)
Tape and Reel
16 Ld SOIC
Tape and Reel
16 Ld SOIC (Pb-free)
Tape and Reel
E16.3
M20.3
68HC68T1MZ
HC68T1M2
-40 to +85
-40 to +85
M20.3
M16.3
HC68T1M2Z
-40 to +85
M16.3
*Add “96” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN1547 Rev 9.00
Decemember 8, 2015
Page 2 of 24
CDP68HC68T1
Absolute Maximum Ratings
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage (V
IN
) . . . . . . . . . . . . . . . . . . . V
SS
-0.3V to V
DD
+0.3V
Current Drain Per Input Pin (Excluding V
DD
and V
SS
I) . . . . . 10mA
Current Drain Per Output Pin I. . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Thermal Information
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
85
35
16 Ld PDIP* (Notes
1, 3)
. . . . . . . . . . .
16 Ld SOIC (Notes
2, 3).
. . . . . . . . . . .
65
26
20 Ld SOIC (Notes
2, 3).
. . . . . . . . . . .
60
26
Maximum Junction Temperature (Plastic) . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range (T
STG
). . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +6.0V
Standby (Timekeeping) Voltage . . . . . . . . . . . . . . . . . +2.2V to +6.0V
Temperature Range
CDP68HC68T1E (PDIP Package) . . . . . . . . . . . . .-40°C to +85°C
CDP68HC68T1M/M2 (SOIC Packages) . . . . . . . .-40°C to +85°C
Input Voltage
Input High . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(0.7 x V
DD
) to V
DD
Input Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to (0.3 x V
DD
)
Serial Clock Frequency (f
SCK
). . . . . . . . . . . . . . . . . . +3.0V to +6.0V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1.
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
2.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379
for details.
3. For
JC
, the “case temp” location is taken at the package top center.
Static Electrical Specifications
At T
A
= -40°C to +85°C, V
DD
= V
BATT
= 5V ±5%, Unless Otherwise Specified.
CDP68HC68T1
PARAMETER
Quiescent Device Current
Output Voltage High Level
Output Voltage Low Level
Output Voltage High Level
Output Voltage Low Level
Input Leakage Current
Three-State Output Leakage Current
Operating Current (Note 5)
(I
D
+ I
B
) V
DD
= V
B
= 5V
Crystal Operation
SYMBOL
I
DD
V
OH
V
OL
V
OH
V
OL
I
IN
I
OUT
32kHz
1MHz
2MHz
4MHz
XTAL IN Clock (Squarewave) (Note 5)
(I
D
+ I
B
) V
DD
= V
S
= 5V
32kHz
1MHz
2MHz
4MHz
Standby Current (Note 5)
V
S
= 3V
Crystal Operation
I
B
32kHz
1MHz
2MHz
4MHz
I
OH
= -1.6mA, V
DD
= 4.5V
I
OL
= 1.6mA, V
DD
= 4.5V
I
OH
10µA,
V
DD
= 4.5V
I
OL
10µA,
V
DD
= 4.5V
TEST CONDITIONS
MIN
-
3.7
-
TYP
(Note 4)
1
-
-
-
-
-
-
0.08
0.5
0.7
1
0.02
0.1
0.2
0.4
20
200
300
500
MAX
10
-
0.4
-
0.1
±1
±10
-
-
-
-
0.024
0.12
0.24
0.5
-
-
-
-
UNITS
µA
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
4.4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FN1547 Rev 9.00
Decemember 8, 2015
Page 3 of 24
CDP68HC68T1
Static Electrical Specifications
At T
A
= -40°C to +85°C, V
DD
= V
BATT
= 5V ±5%, Unless Otherwise Specified.
(Continued)
CDP68HC68T1
PARAMETER
Operating Current (Note 5)
V
DD
= 5V, V
B
= 3V
Crystal Operation
SYMBOL
TEST CONDITIONS
MIN
TYP
(Note 4)
I
D
32kHz
1MHz
2MHz
4MHz
Standby Current (Note 5)
V
B
= 2.2V
Crystal Operation
Input Capacitance
Maximum Rise and Fall Times
(Except XTAL Input and POR Pin 10)
Input Voltage (Line Input Pin Only, Power Sense
Mode)
V
SYS
> V
B
V
T
(For V
B
Not Internally Connected to V
DD
)
Power-On Reset (POR) Pulse Width
NOTES:
4. Typical values are for T
A
= +25°C and nominal V
DD
.
5. Clock out (Pin 1) disabled, outputs open circuited. No serial access cycles.
I
B
32kHz
-
-
-
-
-
0.025
0.08
0.15
0.3
10
I
B
0.015
0.15
0.25
0.4
MAX
-
-
-
-
-
-
UNITS
mA
mA
mA
mA
mA
µA
C
IN
t
r
, t
f
V
IN
= 0, T
A
= +25°C
-
-
-
-
-
2
2
-
12
-
-
pF
µs
µs
V
V
ns
0
-
100
10
1.0
75
Dynamic Electrical Specifications
Bus Timing V
DD
±10%, V
SS
= 0V
DC
, T
A
= -40°C to +85°C
LIMITS (ALL TYPES)
IDENTIFICATION
NUMBER
1
2
3
4
5
7
8
11
12
A
B
C
V
DD
= 3.3V
PARAMETER
Chip Enable Setup Time
Chip Enable After Clock Hold Time
Clock Width High
Clock Width Low
Data In to Clock Setup Time
Clock to Data Propagation Delay
Chip Disable to Output High Z
Output Rise Time
Output Fall Time
Data in After Clock Hold Time
Clock to Data Out Active
Clock Recovery Time
SYMBOL
t
EVCV
t
CVEX
t
WH
t
WL
t
DVCV
t
CVDV
t
EXQZ
t
r
t
f
t
CVDX
t
CVQX
t
REC
MIN
200
250
400
400
200
-
-
-
-
200
-
200
MAX
-
-
-
-
-
200
200
200
200
-
200
-
MIN
100
125
200
200
100
-
-
-
-
100
-
200
V
DD
= 5V
MAX
-
-
-
-
-
100
100
100
100
-
100
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FN1547 Rev 9.00
Decemember 8, 2015
Page 4 of 24
FN1547 Rev 9.00
Decemember 8, 2015
Page 5 of 24
Functional Block Diagram
CE
FREEZE
CIRCUIT
AM - PM AND
HOUR LOGIC
CALENDAR
LOGIC
CDP68HC68T1
LINE
50/60Hz
XTAL IN
XTAL OUT
V
BATT
PRESCALE
SELECT
CLOCK
OUT
INT
V
DD
V
SS
CLOCK
AND
INT
LOGIC
CLOCK
SELECT
OSCILLATOR
PRESCALE
SECOND
MINUTE
HOUR
DAY/DAY
OF WEEK
MONTH
CLOCK
CONTROL
REGISTER
INTERRUPT
CONTROL
REGISTER
COMPARATOR
SECOND
LATCH
MINUTE
LATCH
8-BIT DATA BUS
CDP68HC68T1
YEAR
HOUR
LATCH
LINE
V
SYS
POR
PSE
CPUR
SCK
MISO
MOSI
SERIAL
INTERFACE
POWER
SENSE
CONTROL
INT STATUS
REGISTER
32x8
RAM
FIGURE 1. REAL TIME CLOCK FUNCTIONAL DIAGRAM
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