March 2008
HY[B/I]18T1G400C2[C/F](L)
HY[B/I]18T1G800C2[C/F](L)
HY[B/I]18T1G160C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
Internet Data Sheet
Rev. 1.20
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
Revision History: Rev. 1.20, 2008-03
Adapted internet edition
Corrected parameter tLZ.FQ in chapter 7.2 and parameter tRAS
Previous Revision: Rev. 1.10, 2008-02
Added more producs
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qag_techdoc_A4, 4.20, 2008-01-25
09262007-3YK7-BKKG
2
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 1-Gbit Double-Data-Rate-Two SDRAM offers the following key features:
• Off-Chip-Driver impedance adjustment (OCD) and
• 1.8 V
±
0.1 V Power Supply
1.8 V
±
0.1 V (SSTL_18) compatible I/O
On-Die-Termination (ODT) for better signal quality
• DRAM organizations with 4,8,16 data in/outputs
• Auto-Precharge operation for read and write bursts
• Double Data Rate architecture:
• Auto-Refresh, Self-Refresh and power saving Power-
– two data transfers per clock cycle
Down modes
– eight internal banks for concurrent operation
• Operating temperature range 0 °C to 95 °C
• Programmable CAS Latency: 3, 4, 5 and 6
• Industrial temperature range -40 °C to 95 °C
• Programmable Burst Length: 4 and 8
• Average Refresh Period 7.8
μs
at a
T
CASE
lower
• Differential clock inputs (CK and CK)
than 85 °C, 3.9
μs
between 85 °C and 95 °C
• Bi-directional, differential data strobes (DQS and DQS) are
• Programmable self refresh rate via EMRS2 setting
transmitted / received with data. Edge aligned with read
• Programmable partial array refresh via EMRS2 settings
data and center-aligned with write data.
• DCC enabling via EMRS2 setting
• DLL aligns DQ and DQS transitions with clock
• Full and reduced Strength Data-Output Drivers
• 1KB page size for ×4 and ×8, 2KB page size for ×16
• DQS can be disabled for single-ended data strobe
operation
• Packages: PG-TFBGA-84, PG-TFBGA-60, P-TFBGA-84,
• Commands entered on each positive clock edge, data and
P-TFBGA-60
data mask are referenced to both edges of DQS
• All Speed grades faster than DDR2–400 comply with
• Data masks (DM) for write data
DDR2–400 timing specifications when run at a clock rate
• Posted CAS by programmable additive latency for better
of 200 MHz.
command and data bus efficiency
Rev. 1.20, 2008-03
09262007-3YK7-BKKG
3
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
DDR2
–1.9
–1066F
7–7–7
CL3
–
266
333
400
533
13.125
13.125
40
53.125
15
–25F
–800D
5–5–5
200
266
400
–
–
12.5
12.5
40
52.5
15
–2.5
–800E
6–6–6
200
266
333
400
–
15
15
40
55
17.5
–3S
–667D
5–5–5
200
266
333
–
–
15
15
40
55
18
–3.7
–533C
4–4–4
200
266
266
–
–
15
15
40
55
18.75
Unit
Note
t
CK
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
1)2)
f
CK3
CL4
f
CK4
CL5
f
CK5
f
CK6
CL6
CL7
f
CK7
Min. RAS-CAS-Delay
t
RCD
t
RP
Min. Row Precharge Time
Min. Row Active Time
t
RAS
Min. Row Cycle Time
t
RC
Precharge-All (8 banks) command
t
PREA
period
1) This
t
PREA
value is the minimum value at which this chip will be functional.
2) Precharge-All command for an 8 bank device will equal to
t
RP
+ 1 ×
t
CK
or
t
nRP
+ 1 × nCK, depending on the speed bin,
where
t
nRP
= RU{
t
RP
/
t
CK(avg)
} and
t
RP
is the value for a single bank precharge.
1.2
Description
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 17 bit address bus for ×4 and ×8 organised components
and a 16 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The DDR2 device operates with a 1.8 V
±
0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
The 1-Gbit DDR2 DRAM is a high-speed Double-Data-Rate-
Two CMOS Synchronous DRAM device containing
1,073,741,824 bits and internally configured as an octal bank
DRAM.
The 1-Gbit device is organized as 32 Mbit
×4
I/O
×8
banks or
16 Mbit
×8
I/O
×8
banks or 8 Mbit
×16
I/O
×8
banks chip.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1
for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
Rev. 1.20, 2008-03
09262007-3YK7-BKKG
4
Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F](L)
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
Org. Speed
CAS-RCD-RP
Latencies
2)3)4)
Clock (MHz) Package
Note
5)
Standard Temperature Range (0 °C - +95 °C)
DDR2-1066F( 7-7-7 )
HYB18T1G160C2F-1.9
HYB18T1G400C2F-1.9
HYB18T1G800C2F-1.9
DDR2-800E( 6-6-6 )
HYB18T1G160C2FL-2.5
HYB18T1G400C2FL-2.5
HYB18T1G800C2FL-2.5
HYB18T1G400C2F-2.5
HYB18T1G160C2F-2.5
HYB18T1G800C2F-2.5
DDR2-800D( 5-5-5 )
HYB18T1G400C2F-25F
HYB18T1G800C2F-25F
HYB18T1G160C2F-25F
DDR2-667D( 5-5-5 )
HYB18T1G160C2FL-3S
HYB18T1G400C2FL-3S
HYB18T1G800C2FL-3S
HYB18T1G405C2F-3S
HYB18T1G400C2F-3S
HYB18T1G800C2F-3S
HYB18T1G160C2F-3S
DDR2-533C( 4-4-4 )
HYB18T1G160C2FL-3.7
HYB18T1G400C2FL-3.7
HYB18T1G800C2FL-3.7
HYB18T1G160C2F-3.7
HYB18T1G400C2F-3.7
HYB18T1G800C2F-3.7
×16
×4
×8
×16
×4
×8
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-533C
4-4-4
4-4-4
4-4-4
4-4-4
4-4-4
4-4-4
266
266
266
266
266
266
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
×16
×4
×8
×4
×4
×8
×16
DDR2-667D
DDR2-667D
DDR2-667D
DDR2-667D
DDR2-667D
DDR2-667D
DDR2-667D
5-5-5
5-5-5
5-5-5
5-5-5
5-5-5
5-5-5
5-5-5
333
333
333
333
333
333
333
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×4
×8
×16
DDR2-800D
DDR2-800D
DDR2-800D
5-5-5
5-5-5
5-5-5
400
400
400
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×16
×4
×8
×4
×16
×8
DDR2-800E
DDR2-800E
DDR2-800E
DDR2-800E
DDR2-800E
DDR2-800E
6-6-6
6-6-6
6-6-6
6-6-6
6-6-6
6-6-6
400
400
400
400
400
400
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
×16
×4
×8
DDR2-1066F 7-7-7
DDR2-1066F 7-7-7
DDR2-1066F 7-7-7
533
533
533
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
Rev. 1.20, 2008-03
09262007-3YK7-BKKG
5
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