SAF7118
Multistandard video decoder with adaptive comb filter and
component video input
Rev. 04 — 4 July 2008
Product data sheet
1. General description
The SAF7118 is a video capture device that, due to its improved comb filter performance,
is suitable for various applications such as in-car video reception, in-car entertainment or
in-car navigation.
The SAF7118 is a combination of a four-channel analog preprocessing circuit including
source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC) with
succeeding decimation filters from 27 MHz to 13.5 MHz data rate. Each preprocessing
channel comes with an automatic clamp and gain control. The SAF7118 combines a
Clock Generation Circuit (CGC), a digital multistandard decoder containing
two-dimensional chrominance/luminance separation by an adaptive comb filter and a high
performance scaler, including variable horizontal and vertical up and downscaling and a
brightness, contrast and saturation control circuit.
It is a highly integrated circuit for desktop video and similar applications. The decoder is
based on the principle of line-locked clock decoding and is able to decode the color of
PAL, SECAM and NTSC signals into ITU 601 compatible color component values. The
SAF7118 accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources,
including weak and distorted signals as well as baseband component signals Y-P
B
-P
R
or
RGB. An expansion port (X port) for digital video (bidirectional half duplex, D1 compatible)
is also supported to connect to MPEG or a video phone codec. At the so called image port
(I port) the SAF7118 supports 8-bit or 16-bit wide output data with auxiliary reference data
for interfacing to VGA controllers.
The target application for the SAF7118 is to capture and scale video images, to be
provided as a digital video stream through the image port of a VGA controller, for capture
to system memory, or just to provide digital baseband video to any picture improvement
processing.
The SAF7118 also provides a means for capturing the serially coded data in the Vertical
Blanking Interval (VBI) data. Two principal functions are available:
1. To capture raw video samples, after interpolation to the required output data rate, via
the scaler
2. A versatile data slicer (data recovery) unit
The SAF7118 also incorporates field-locked audio clock generation. This function ensures
that there is always the same number of audio samples associated with a field, or a set of
fields. This prevents the loss of synchronization between video and audio during capture
or playback.
All of the ADCs may be used to digitize a Vestigial Side Band (VSB) signal for subsequent
decoding; a dedicated output port and a selectable VSB clock input is provided.
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
The circuit is I
2
C-bus controlled (full write/read capability for all programming registers, bit
rate up to 400 kbit/s).
2. Features
2.1 Video acquisition/clock
I
Up to sixteen analog CVBS, split as desired (all of the CVBS inputs optionally can be
used to convert e.g. VSB signals)
I
Up to eight analog Y + C inputs, split as desired
I
Up to four analog component inputs, with embedded or separate sync, split as desired
I
Four on-chip anti-aliasing filters in front of the ADCs
I
Automatic Clamp Control (ACC) for CVBS, Y and C (or VSB) and component signals
I
Switchable white peak control
I
Four 9-bit low noise CMOS ADCs running at twice the oversampling rate (27 MHz)
I
Fully programmable static gain or Automatic Gain Control (AGC), matching to the
particular signal properties
I
On-chip line-locked clock generation in accordance with
“ITU 601”
I
Requires only one crystal (32.11 MHz or 24.576 MHz) for all standards
I
Horizontal and vertical sync detection
2.2 Video decoder
I
Digital Phase-Locked Loop (PLL) for synchronization and clock generation from all
standards and non-standard video sources e.g. consumer grade VTR
I
Automatic detection of any supported color standard
I
Luminance and chrominance signal processing for PAL B, G, D, H, I and N,
combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
I
Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation,
also with VTR signals
N
Increased luminance and chrominance bandwidth for all PAL and NTSC standards
N
Reduced cross color and cross luminance artefacts
I
PAL delay line for correcting PAL phase errors
I
Brightness Contrast Saturation (BCS) adjustment, separately for composite and
baseband signals
I
User programmable sharpness control
I
Detection of copy-protected signals according to the Macrovision standard, indicating
level of protection
I
Independent gain and offset adjustment for raw data path
2.3 Component video processing
I
I
I
I
RGB component inputs
Y-P
B
-P
R
component inputs
Fast blanking between CVBS and synchronous component inputs
Digital RGB to Y-C
B
-C
R
matrix
SAF7118_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
2 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
2.4 Video scaler
I
Horizontal and vertical downscaling and upscaling to randomly sized windows
I
Horizontal and vertical scaling range: variable zoom to
1
⁄
64
(icon) (it should be noted
that the H and V zoom are restricted by the transfer data rates)
I
Anti-alias and accumulating filter for horizontal scaling
I
Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing
(6-bit phase accuracy)
I
Horizontal phase correct up and downscaling for improved signal quality of scaled
data, especially for compression and video phone applications, with 6-bit phase
accuracy (1.2 ns step width)
I
Two independent programming sets for scaler part, to define two ‘ranges’ per field or
sequences over frames
I
Fieldwise switching between decoder part and expansion port (X port) input
I
Brightness, contrast and saturation controls for scaled outputs
2.5 VBI data decoder and slicer
I
Versatile VBI data decoder, slicer, clock regeneration and byte synchronization e.g. for
World Standard Teletext (WST), North American Broadcast Text System (NABTS),
closed caption, Wide Screen Signalling (WSS), etc.
2.6 Audio clock generation
I
Generation of a field-locked audio master clock to support a constant number of audio
clocks per video field
I
Generation of an audio serial and left/right (channel) clock signal
2.7 Digital I/O interfaces
I
Real-time signal port (R port), inclusive continuous line-locked reference clock and
real-time status information supporting RTC level 3.1 (refer to document
“RTC Functional Specification”
for details)
I
Bidirectional expansion port (X port) with half duplex functionality (D1), 8-bit Y-C
B
-C
R
:
N
Output from decoder part, real-time and unscaled
N
Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
I
Video image port (I port) configurable for 8-bit data (extension to 16-bit possible) in
master mode (own clock), or slave mode (external clock), with auxiliary timing and
handshake signals
I
Discontinuous data streams supported
I
32-word
×
4-byte FIFO register for video output data
I
28-word
×
4-byte FIFO register for decoded VBI data output
I
Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 Y-C
B
-C
R
output
I
Scaled 8-bit luminance only and raw CVBS data output
I
Sliced, decoded VBI data output
2.8 Miscellaneous
I
Power-on control
I
5 V tolerant digital inputs and I/O ports
SAF7118_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
3 of 175
NXP Semiconductors
SAF7118
Multistandard video decoder with adaptive comb filter
I
Software controlled power saving standby modes supported
I
Programming via serial I
2
C-bus, full read back ability by an external controller, bit rate
up to 400 kbit/s
I
Boundary scan test circuit complies with the
“IEEE Std. 1149.b1 - 1994”.
3. Applications
I
I
I
I
General industrial video applications
In-car TV reception
In-car entertainment
In-car navigation platforms
4. Quick reference data
Table 1.
Symbol
V
DDD
V
DDA
T
amb
P
tot(A+D)
Quick reference data
Parameter
digital supply voltage
analog supply voltage
ambient temperature
total power dissipation analog and
digital part
component mode
[1]
Conditions
Min
3.0
3.1
−40
-
Typ
3.3
3.3
-
1105
Max
3.6
3.5
+85
1350
Unit
V
V
°C
mW
[1]
8-bit image port output mode, expansion port is 3-stated.
5. Ordering information
Table 2.
Ordering information
Package
Name
SAF7118EH
SAF7118H
HBGA156
QFP160
Description
plastic thermal enhanced ball grid array package; 156 balls;
body 15
×
15
×
1.15 mm; heatsink
plastic quad flat package; 160 leads (lead length 1.6 mm);
body 28
×
28
×
3.4 mm; high stand-off height
Version
SOT807-1
SOT322-2
Type number
SAF7118_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 July 2008
4 of 175
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Product data sheet
Rev. 04 — 4 July 2008
© NXP B.V. 2008. All rights reserved.
SAF7118_4
6. Block diagram
NXP Semiconductors
ADP[8:0]
CLKEXT
CE
RES
DNC0 to DNC20
SDA
SCL
INT_A
EXMCLR
AD PORT
CONTROL
I
2
C-BUS REGISTER MAP
FIRST TASK I
2
C-BUS REGISTER MAP SCALER
SECOND TASK I
2
C-BUS REGISTER MAP SCALER
FSW
AI11
AI12
AI13
AI14
AI1D
AI21
AI22
AI23
AI24
AI2D
AI31
AI32
AI33
AI34
AI3D
AI41
AI42
AI43
AI44
AI4D
AOUT
AGND
AGNDA
POWER-ON CONTROL
POWER SUPPLY
VIDEO
CLOCK
GPO
CRYSTAL
FAST SWITCH DELAY
R
G
B
ANALOG2
and
ADC2
ANALOG INPUT CONTROL
COMPONENTS
PROCESSING
RAW
C
B
C
CHROMINANCE
PROCESSING
C
R
Y
C
B
DECODER OUTPUT CONTROL
ANALOG1
and
ADC1
SCALER EVENT CONTROLLER
VERTICAL SCALING
HORIZONTAL
FINE (PHASE) SCALING
C
R
LINE FIFO BUFFER
S
FIR PREFILTER
PRESCALER
BCS SCALER
OUTPUT FORMATTER I PORT
VIDEO FIFO
Y-C
B
-C
R
IGP1
IGP0
IGPV
IGPH
IPD[7:0]
Multistandard video decoder with adaptive comb filter
ANALOG3
and
ADC3
COMB FILTER
SAF7118
RAW
Y-C
B
-C
R
TEXT
FIFO
VBI DATA SLICER
Y
S
LUMINANCE
PROCESSING
S
S
SYNCHRONIZATION
Y
ICLK
IDQ
ITRDY
ITRI
ANALOG4
and
ADC4
S
C
B
-C
R
Y-C
B
-C
R
, S
X PORT
H PORT
AUDIO
CLOCK
BOUNDARY
SCAN
C
B
-C
R
VIDEO/TEXT ARBITER
SAF7118
V
SSA
V
SSD
V
DDA
V
DD(xtal)
LLC2 RTS0 RTCO XTALI XRDY XCLK
AMXCLK ALRCLK TDO
TMS
XRH
XTRI
TRST
V
SS(xtal)
V
DDD
LLC
mbl751
RTS1 XTALO XTOUT XPD[7:0] XDQ
AMCLK ASCLK
TDI
TCK
HPD[7:0]
XRV
5 of 175
Fig 1.
Block diagram
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