24AA04/08
4K/8K 1.8V CMOS Serial EEPROMs
FEATURES
• Single supply with operation down to 1.8V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
- 3
µ
A standby current typical at 1.8V
• Organized as 2 or 4 blocks of 256 bytes
(2 x 256 x 8) or (4 x 256 x 8)
• Two wire serial interface bus, I
2
C
™
compatible
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 100 kHz (1.8V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
•
1,000,000 ERASE/WRITE cycles guaranteed
*
• Data retention > 200 years
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature ranges
- Commercial: 0˚C to +70˚C
PACKAGE TYPE
DIP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
24AA04/08
8-Lead
SOIC
A0
A1
A2
V
SS
1
2
8
7
V
CC
WP
SCL
SDA
24AA04/08
3
4
6
5
14-Lead
SOIC
NC
A0
A1
NC
A2
V
SS
NC
1
2
3
14
13
12
NC
V
CC
WP
NC
SCL
SDA
NC
4
24AA04/08
11
5
6
7
10
9
8
DESCRIPTION
The Microchip Technology Inc. 24AA04/08 is a 4K bit or
8K bit Electrically Erasable PROM. The device is orga-
nized as 2 or 4 blocks of 256 x 8 bit memory with a two
wire serial interface. Low voltage design permits oper-
ation down to 1.8 volts with standby and active currents
of only 3
µ
A and 1 mA respectively. The 24AA04/08
also has a page-write capability for up to 16 bytes of
data. The 24AA04/08 is available in the standard 8-pin
DIP and both 8-lead and 14-lead surface mount SOIC
packages.
BLOCK DIAGRAM
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
EEPROM ARRAY
XDEC
PAGE LATCHES
SDA
SCL
YDEC
V
CC
V
SS
SENSE AMP
R/W CONTROL
*Future: 10,000,000 E/W cycles guaranteed
I
2
C
is a trademark of Philips Corporation
©
1995 Microchip Technology Inc.
DS21053D-page 1
24AA04/08
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
TABLE 1-1:
Name
V
SS
SDA
SCL
WP
Vcc
A0, A1, A2
PIN FUNCTION TABLE
Function
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+1.8V to 5.5V Power Supply
No Internal Connection
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
....-0.6V to VCC +1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied ......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins
......................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +1.8V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Parameter
Sym
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
I
CC
W
RITE
I
CC
R
EAD
Min
.7 V
CC
—
.05 V
CC
—
-10
-10
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
0.5
—
0.05
Max
—
.3 V
CC
—
.40
10
10
10
3
—
1
—
100
30
—
Units
V
V
V
V
µ
A
µ
A
pF
mA
mA
mA
mA
µ
A
µ
A
µ
A
Note 1
I
OL
= 3.0 mA, V
CC
= 1.8V
V
IN
= .1V to V
CC
V
OUT
= .1V to V
CC
V
CC
= 5.0V (Note 1)
Tamb = 25˚C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 1.8V, SCL = 100 kHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 1.8V, SCL = 100 kHz
V
CC
= 5.5V, SDA=SCL=V
CC
V
CC
= 3.0V, SDA=SCL=V
CC
V
CC
= 1.8V, SDA=SCL=V
CC
Conditions
WP, SCL and SDA pins:
High level input voltage
Low Level input voltage
Hysteresis of Schmitt trigger
inputs
Low level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
Standby current
I
CCS
3
Note 1: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU:STA
SDA
T
HD:STA
T
SU:STO
START
STOP
DS21053D-page 2
©
1995 Microchip Technology Inc.
24AA04/08
TABLE 1-3:
AC CHARACTERISTICS
Standard Mode
Parameter
Symbol
Min
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
F
CLK
T
HIGH
T
LOW
T
R
T
F
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
—
—
—
Max
100
—
—
1000
300
—
—
—
—
—
3500
—
250
50
10
V
CC
= 4.5-5.5V
Fast Mode
Min
—
600
1300
—
—
600
600
0
100
600
—
1300
20 + 0.1
C
B
—
—
Max
400
—
—
300
300
—
—
—
—
—
900
—
250
50
10
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note 1
Time the bus must be free before
a new transmission can start
Note 2, C
B
≤
100 pF
Note 3
Byte or Page mode
Note 2
Note 2
After this period the first clock
pulse is generated
Only relevant for repeated
START condition
Units
Remarks
START condition hold time T
HD
:
STA
START condition setup
time
Data input hold time
Data input setup time
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
STOP condition setup time T
SU
:
STO
Output valid from clock
Bus free time
Output fall time from V
IH
min to V
IL
max
Input filter spike suppres-
sion (SDA and SCL pins)
Write cycle time
T
AA
T
BUF
T
OF
T
SP
T
WR
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Note 2: Not 100% tested. C
B
= total capacitance of one bus line in pF.
Note 3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a T
I
specification for standard operation.
FIGURE 1-2:
BUS TIMING DATA
t
F
t
HIGH
t
LOW
t
R
SCL
t
SU:STA
t
SDA
IN
t
SP
t
AA
SDA
OUT
t
t
BUF
AA
HD:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
©
1995 Microchip Technology Inc.
DS21053D-page 3
24AA04/08
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24AA04/08 supports a bidirectional two wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24AA04/08 works as slave. Both, master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (see Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note:
The 24AA04/08 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
FIGURE 3-1:
(A)
SCL
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
START CONDITION
ADDRESS
DATA ALLOWED
OR
TO CHANGE
ACKNOWLEDGE
VALID
STOP
CONDITION
DS21053D-page 4
©
1995 Microchip Technology Inc.
24AA04/08
4.0
4.1
BUS CHARACTERISTICS
Device Addressing and Operation
5.0
5.1
WRITE OPERATION
Byte Write
A control byte is the first byte received following the
start condition from the master device. The control
byte consists of a four bit control code, for the
24AA04/08 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the block select bits (B2, B1, B0). B2 is a don't care for
both the 24AA04 and 24AA08; B1 is a don't care for
the 24AA04. They are used by the master device to
select which of the two or four 256 word blocks of mem-
ory are to be accessed. These bits are in effect the
most significant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24AA04/08 monitors
the SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24AA04/08 will select a
read or write operation.
Operation
Read
Write
Control
Code
1010
1010
Block Select
Block Address
Block Address
R/W
1
0
Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24AA04/08. After
receiving another acknowledge signal from the
24AA04/08 the master device will transmit the data
word to be written into the addressed memory location.
The 24AA04/08 acknowledges again and the master
generates a stop condition. This initiates the internal
write cycle, and during this time the 24AA04/08 will not
generate acknowledge signals (see Figure 5-1).
5.2
Page Write
FIGURE 4-1:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W
A
The write control byte, word ad dress and the first data
byte are transmitted to the 24AA04/08 in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to sixteen data bytes to
the 24AA04/08 which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than six-
teen words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 8-1).
1
0
1
0
X
B1
B0
X = don't care, B1 is don't care for 24AA04
FIGURE 5-1:
BYTE WRITE
S
T
A
R
T
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
CONTROL
BYTE
WORD
ADDRESS
DATA
S
T
O
P
P
©
1995 Microchip Technology Inc.
DS21053D-page 5
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