HY62SF8400A Series
512Kx8bit full CMOS SRAM
DESCRIPTION
The HY62SF8400A is a high speed, super low
power and 4Mbit full CMOS SRAM organized as
512K words by 8bits. The HY62SF8400A uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
FEATURES
•
Fully static operation and Tri-state output
•
TTL compatible inputs and outputs
•
Battery backup
-. 1.2V(min) data retention
•
Standard pin configuration
-. 36-ball uBGA
Product No.
Voltage
(V)
Speed (ns)
Operation
Current/Icc(mA)
3
3
HY62SF16400A
1.7~2.3
85/100/120
HY62SF16400A-I 1.7~2.3
85/100/120
Note 1. Blank : Commercial, I : Industrial
2. Current value is max.
Standby
Current(uA)
LL
SL
10
2
10
2
Temperature
(°C)
0~70
-40~85(I)
PIN CONNECTION
A0
IO5
IO6
Vss
Vcc
IO7
IO8
A9
A18
A17
A15
A13
A1
A2
CS2
/WE
NC
A3
A4
A5
A6
A7
A8
A0
BLOCK DIAGRAM
ROW
DECODER
IO1
COLUMN
DECODER
I/O1
SENSE AMP
IO2
ADD INPUT
BUFFER
PRE DECODER
DATA I/O
BUFFER
Vcc
Vss
IO3
IO4
A14
/CS1
CS2
/OE
/WE
A18
MEMORY ARRAY
256K x 8
WRITE DRIVER
BLOCK
DECODER
/OE /CS1 A16
A10 A11
A12
I/O8
uBGA
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Pin Name
A0 ~ A18
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Address Input
Data Input/Output
Power(1.7V~2.3V)
Ground
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.05 / Jun.00
Hyundai Semiconductor
HY62SF8400A Series
ORDERING INFORMATION
Part No.
HY62SF8400ALLM
HY62SF8400ASLM
HY62SF8400ALLM-I
HY62SF8400ASLM-I
Speed
85/100/120
85/100/120
85/100/120
85/100/120
Power
LL-part
SL-part
LL-part
SL-part
Temp
.
Package
uBGA
uBGA
uBGA
uBGA
I
I
Note 1. Blank : Commercial, I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
V
IN,
V
OUT
Vcc
T
A
T
STG
P
D
T
SOLDER
Parameter
Input/Output Voltage
Power Supply
Operating Temperature
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
Rating
-0.3 to 2.6
-0.3 to 3.6
0 to 70
-40 to 85
-55 to 150
1.0
260
•
10
Unit
V
V
°C
°C
°C
W
°C•sec
Remark
HY62SF8400A
HY62SF8400A-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1
H
X
L
L
L
CS2
X
L
H
H
H
/WE
X
X
H
H
L
/OE
X
X
H
L
X
MODE
Deselected
Deselected
Output Disabled
Read
Write
I/O OPERATION
High-Z
High-Z
High-Z
Dout
Din
Supply Current
Standby
Standby
Active
Active
Active
Note:
1. H=V
IH
, L=V
IL
, X=don't care (V
IL or
V
IH
)
Rev.05 / Jun.00
2
HY62SF8400A Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
1.7
0
1.4
-0.3
1.
.
Typ
1.8
0
-
-
Max.
2.3
0
Vcc+0.3
0.4
Unit
V
V
V
V
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns
2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
T
A
= 0°C to 70°C / -40°C to 85°C (I)
Sym
Parameter
I
LI
Input Leakage Current
I
LO
Output Leakage Current
Test Condition
Vss < V
IN
< Vcc
Vss < V
OUT
< Vcc,
/CS1 = V
IH
or CS2=V
IL
or
/
OE
=
V
IH
or /WE = V
IL
/CS1 = V
IL
, CS2=V
IH
,
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
/CS1 = V
IL,
CS2 = V
IH
,
V
IN
= V
IH
or V
IL,
Cycle Time = Min,
100% Duty, I
I/O =
0mA
/CS1 < 0.2V
,
CS2 > Vcc-0.2V,
V
IN
< 0.2V or V
IN
> Vcc-0.2V
,
Cycle Time = 1us,
100% Duty, I
I/O =
0mA
/CS1 = V
IH
or CS2 = V
IL
/CS1 > Vcc - 0.2V or
SL
CS2 < Vss + 0.2V
LL
I
OL
= 0.1mA
I
OH =
-0.1mA
Min
-1
-1
Typ
1.
-
-
Max
1
1
Unit
uA
uA
Icc
I
CC1
Operating Power Supply Current
Average Operating Current
3
20
mA
mA
3
mA
I
SB
I
SB1
V
OL
V
OH
Standby Current
(TTL Input)
Standby Current
(CMOS Input)
Output Low
Output High
-
1.6
0.5
0.5
-
-
0.3
2
10
0.2
-
mA
uA
uA
V
V
Note
1. Typical values are at Vcc = 1.8V T
A
= 25°C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25°C, f= 1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance(Add, /CS1,CS2, /WE, /OE)
C
OUT
Output Capacitance(I/O)
Note : These parameters are sampled and not 100% tested
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
8
10
Unit
pF
pF
Rev.05 / Jun.00
3
HY62SF8400A Series
AC CHARACTERISTICS
T
A
= 0°C to 70°C / -40°C to 85°C (I), unless otherwise specified
85ns
Parameter
# Symbol
Min.
Max.
READ CYCLE
1
tRC
Read Cycle Time
85
-
2
tAA
Address Access Time
-
85
3
tACS
Chip Select Access Time
-
85
4
tOE
Output Enable to Output Valid
-
40
5
tCLZ
Chip Select to Output in Low Z
10
-
6
tOLZ
Output Enable to Output in Low Z
5
-
7
tCHZ
Chip Deselection to Output in High Z
0
30
8
tOHZ
Out Disable to Output in High Z
0
30
9
tOH
Output Hold from Address Change
10
-
WRITE CYCLE
10 tWC
Write Cycle Time
85
-
11 tCW
Chip Selection to End of Write
70
-
12 tAW
Address Valid to End of Write
70
-
13 tAS
Address Set-up Time
0
-
14 tWP
Write Pulse Width
60
-
15 tWR
Write Recovery Time
0
-
16 tWHZ
Write to Output in High Z
0
25
17 tDW
Data to Write Time Overlap
35
-
18 tDH
Data Hold from Write Time
0
-
19 tOW
Output Active from End of Write
5
-
100ns
Min.
Max.
100
-
-
-
20
5
0
0
15
100
80
80
0
70
0
0
40
0
10
-
100
100
50
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
120ns
Min
Max.
120
-
-
-
20
10
0
0
15
100
100
100
0
85
0
0
50
0
10
-
120
120
60
-
-
40
40
-
-
-
-
-
-
-
35
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
T
A
= 0°C to 70°C / -40°C to 85°C (I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 1.6V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
0.9V
Output Load
CL = 30pF + 1TTL Load
AC TEST LOADS
V
TM
=1.8V
4091 Ohm
D
OUT
CL(1)
3273 Ohm
Note
1. Including jig and scope capacitance:
Rev.05 / Jun.00
4
HY62SF8400A Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC
ADDR
tAA
tACS
/CS1
tOH
CS2
tCHZ
(3)
/OE
tOLZ
(3)
Data
Out
High-Z
tCLZ
(3)
Data Valid
tOE
tOHZ
(3)
READ CYCLE 2(Note 1,2,4)
tRC
ADDR
tAA
tOH
Data
Out
Previous Data
Data Valid
tOH
READ CYCLE 3(Note 1,2,4)
/CS1
CS2
tACS
tCLZ
(3)
Data
Out
Data Valid
tCHZ
(3)
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low /CS1 and CS2 are in active status.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active
Rev.05 / Jun.00
5
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