88SE9182 R1.2
Two-Lane PCIe 2.0 to Two-Port 6
Gbps SATA I/O Controller
Datasheet
Doc No. MV-S108871-U0 Rev. A
October 4, 2018
Document Classification: Public
Marvell.
Moving Forward Faster
88SE9182 R1.2 Two-Lane PCIe 2.0 to Two-Port 6 Gbps SATA I/O Controller
Datasheet
For more information, visit our website at:
www.marvell.com
This Document And The Information Furnished In This Document Are Provided "As Is" Without Any Warranty.
Marvell Expressly Disclaims And Makes No Warranties Or Guarantees, Whether Express, Oral, Implied,
Statutory, Arising By Operation Of Law, Or As A Result Of Usage Of Trade, Course Of Dealing, Or Course Of
Performance, Including The Implied Warranties Of Merchantability And Fitness For Particular Purpose And
Non-infringement.
This document, including any software or firmware included or referenced in this document is owned by
Marvell. The information furnished in this document is provided for reference purposes only for use with
Marvell products. It is the user's own responsibility to design or build products with the information. Marvell
products are not authorized for use as critical components in medical devices, military systems, life or critical
support devices, or related systems. Marvell is not liable, in whole or in part, and the user shall indemnify and
hold Marvell harmless for any claim, damage, or other liability related to any such use of Marvell products.
Marvell and the Marvell logo are registered trademarks of Marvell. For a more complete listing of Marvell
trademarks, visit www.marvell.com.
Copyright © 2018. Marvell International Ltd. All rights reserved.
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Copyright © 2018 Marvell
October 4, 2018
Doc No. MV-S108871-U0 Rev. A
Document Classification: Public
Ordering Information
ORDERING INFORMATION
Ordering Part Numbers and Package Markings
The following figure shows the ordering part numbering scheme for the 88SE9182 part. For complete
ordering information, contact your Marvell FAE or sales representative.
Sample Ordering Part Number
88XXXXX - XX - XXX - C000 - XXXX
Part Number
Extended Part Number
Product Revision
Custom Code
Package Code
3-character
alphabetic code
such as BCC, TEH
Custom Code
(optional )
Custom Code
Temperature Code
C = Commercial
I = Industrial
Environmental Code
+ = RoHS 0/6
– = RoHS 5/6
1 = RoHS 6/6
2 = Green)
The standard ordering part numbers for the respective solutions are indicated in the following table.
Ordering Part Numbers
Part Number
88SE9182A2-NNX2C000
88SE9182A2-NNX2I000
88SE9182A2-NNX2A000
Description
56-Pin QFN 7 mm × 7 mm, PCIe 2.0 x2 to two 6 Gbps SATA I/O Controller
56-Pin Industrial Grade QFN 7 mm × 7 mm, PCIe 2.0 x2 to two 6 Gbps SATA I/O
Controller
56-Pin Automotive Grade QFN 7 mm × 7 mm, PCIe 2.0 x2 to two 6 Gbps SATA
I/O Controller *
The next figure shows a typical Marvell package marking.
88SE9182 Package Marking and Pin 1 Location
Marvell Logo
Country of origin
(contained in the mold ID or
marked as the last line on
the package)
Part number, package code environmental code
e
,
XXXXX = Part number
AAA = Package code
e = Environmental code
(+ = RoHS 0/6, no code = RoHS 5/6,
1 = RoHS 6/6, 2 = Green)
Date code, custom code, assembly plant code
YYWW = Date code (YY = year, WW = Work Week)
xx = Custom code or die revision
@ = Assembly plant code
88XXXXX-AAAe
Lot Number
YYWW xx@
Country of Origin
Pin 1 location
Note:
The above drawing is not drawn to scale. The location of markings is approximate. Add-on marks are not
represented. Flip chips vary widely in their markings and flip chip examples are not shown here. For flip chips, the
markings may be omitted per customer requirement.
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Copyright © 2018 Marvell
October 4, 2018
Doc No. MV-S108871-U0 Rev. A
Document Classification: Public
88SE9182 R1.2 Two-Lane PCIe 2.0 to Two-Port 6 Gbps SATA I/O Controller
Datasheet
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Copyright © 2018 Marvell
October 4, 2018
Doc No. MV-S108871-U0 Rev. A
Document Classification: Public
Change History
CHANGE HISTORY
The following table identifies the document change history for Rev. A.
Document Changes *
Location
Global
Page
3-5
Page
4-1
Type
Update
Update
Update
Description
Removed “preliminary” designation from titles and page headers.
Updated the description for CLKP and CLKN in Table 3-2,
PCIe
Interface Signals.
Updated the following in Chapter 4,
Layout Guidelines:
The information in this chapter is preliminary. Please consult with
Marvell Semiconductor design and application engineers before
starting your PCB design.
to
Note:
The information in this chapter is intended only to provide
guidelines, and is not meant to restrict the customer from exercising
discretion in implementing board designs. In cases where it is deemed
necessary to deviate from the guidelines, Marvell recommends that
customers consult with the Marvell FAEs to ensure that the performance
of the Marvell product is not compromised.
* The type of change is categorized as: Parameter, Revision, or Update. A Parameter change is a change to a spec value, a Revision
change is one that originates from the chip Revision Notice, and an Update change includes all other document updates.
Date
April 4, 2018
April 4, 2018
April 6, 2018
v
Copyright © 2018 Marvell
October 4, 2018
Doc No. MV-S108871-U0 Rev. A
Document Classification: Public
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