D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
SN54LV164, SN74LV164
8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS
SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
D
EPIC
(Enhanced-Performance Implanted
D
D
D
CMOS) 2-µ Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
> 2 V at V
CC
, T
A
= 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
SN54LV164 . . . J OR W PACKAGE
SN74LV164 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
D
D
A
B
Q
A
Q
B
Q
C
Q
D
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
Q
H
Q
G
Q
F
Q
E
CLR
CLK
SN54LV164 . . . FK PACKAGE
(TOP VIEW)
B
A
NC
V
CC
Q
H
Q
A
NC
Q
B
NC
Q
C
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
description
These 8-bit parallel-out serial shift registers are
designed for 2.7-V to 5.5-V V
CC
operation.
Q
G
NC
Q
F
NC
Q
E
The ’LV164 feature AND-gated serial (A and B)
inputs and an asynchronous clear (CLR) input.
The gated serial inputs permit complete control
NC − No internal connection
over incoming data as a low at either input inhibits
entry of the new data and resets the first flip-flop
to the low level at the next clock pulse. A high-level
input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can
be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking
occurs on the low-to-high-level transition of the clock (CLK) input.
The SN74LV164 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV164 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV164 is characterized for operation from −40°C to 85°C.
Q
D
GND
NC
CLK
CLR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
Copyright
1996, Texas Instruments Incorporated
•
•
1
SN54LV164, SN74LV164
8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS
SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
FUNCTION TABLE
INPUTS
CLR
L
H
H
H
H
CLK
X
L
↑
↑
↑
A
X
X
H
L
X
B
X
X
H
X
L
QA
L
QA0
H
L
L
OUTPUTS
QB . . . QH
L
QB0
QAn
QAn
QAn
L
QH0
QGn
QGn
QGn
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state inputs conditions were
established
QAn, QGn = the level of QA or QG before the most recent
↑
transition of the clock: indicates a 1-bit shift
logic symbol
†
CLR
CLK
9
8
SRG8
R
C1/
A
B
1
2
&
1D
3
4
5
6
10
11
12
13
QA
QB
QC
QD
QE
QF
QG
QH
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, DB, J, PW, and W packages.
logic diagram (positive logic)
CLK
8
A
B
1
2
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
CLR
9
3
QA
4
QB
5
QC
6
QD
10
QE
11
QF
12
QG
13
QH
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
SN54LV164, SN74LV164
8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS
SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
typical clear, shift, and clear sequences
CLK
Serial Inputs
A
B
CLR
QA
QB
QC
Outputs
QD
QE
QF
QG
QH
Clear
Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Maximum power dissipation at T
A
= 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . 1.25 W
DB or PW package . . . . . . . . . . . . . 0.5 W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
3
SN54LV164, SN74LV164
8 BIT PARALLEL OUT SERIAL SHIFT REGISTERS
SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996
recommended operating conditions (see Note 4)
SN54LV164
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0
−55
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
0
0
2.7
2
3.15
0.8
1.65
VCC
VCC
−6
−12
6
12
100
125
0
−40
0
0
MAX
5.5
SN74LV164
MIN
2.7
2
3.15
0.8
1.65
VCC
VCC
−6
−12
6
12
100
85
mA
ns/V
°C
mA
V
V
V
V
MAX
5.5
UNIT
V
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100
µA
IOH = −6 mA
IOH = −12 mA
IOL = 100
µA
VOL
IOL = 6 mA
IOL = 12 mA
VI = VCC or GND
VI = VCC or GND,
IO = 0
VCC†
MIN to MAX
3V
4.5 V
MIN to MAX
3V
4.5 V
3.6 V
II
ICC
nI
CC
Ci
5.5 V
3.6 V
5.5 V
3 V to 3.6 V
3.3 V
VI = VCC or GND
5V
2.5
3
One input at VCC − 0.6 V,
Other inputs at VCC or GND
SN54LV164
MIN
TYP
MAX
SN74LV164
MIN
TYP
MAX
UNIT
VOH
VCC − 0.2
2.4
3.6
0.2
0.4
0.55
±1
±1
20
20
500
VCC − 0.2
2.4
3.6
0.2
0.4
0.55
±1
±1
20
20
500
2.5
3
V
V
µA
A
µA
A
µA
pF
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
