CM3107
2 Amp Source/ Sink Bus Termination Regulator
for DDR Memory and Front Side Bus Applications
Features
•
•
•
•
•
•
•
•
•
Ideal for Intel 865 Front Side Bus V
TT
and DDR
V
TT
applications
Sinks and sources 2 Amps
Over current protection
Over temperature protection
Integrated power MOSFETs
Excellent accuracy (0.5% load regulation)
Selectable output (1.225V/1.45V or V
DDQ
/2)
8-lead SOIC and PSOP packages
Lead-free versions available
Product Description
The CM3107 is a sinking and sourcing regulator specif-
ically designed for series-parallel bus termination for
high-speed chip set busses as well as DDR memory
systems. It can source and sink current up to 2.0A with
a load regulation of 0.5%. The V
TT
output voltage is
selectable by V
DDQ
SEL and FSBSEL pins. The
V
DDQ
SEL pin controls whether the CM3107 is in DDR
memory mode with V
TT
=V
DDQ
/2, or in FSB mode. In
FSB mode, FSBSEL controls whether V
TT
is 1.225V or
1.45V. This allows the same chip to be used in two dif-
ferent circuits on an Intel 865-based motherboard.
The CM3107 provides over current and over tempera-
ture protection, which protect the chip from excessive
heating due to high current and high temperature. A
shutdown capability using an external transistor
reduces power consumption and provides a high
impedance output.
The CM3107 is housed in 8-lead SOIC and PSOP
packages and is available with optional lead-free finish-
ing.
Applications
•
•
•
•
Intel 865/845 Front Side Bus termination
Single and dual DDR memory termination
Active termination buses
Graphics card DDR memory termination
Simplified Electrical Schematic
V
CC
V
DDQ
SEL FSBSEL
V
DDQ
50K
Over Temp
Over Current
Reference
Output
Select
Driver
V
REF
OUT
IN
V
TT
50K
Buffer
V
SENSE
GND
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
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www.calmicro.com
1
CM3107
PACKAGE / PINOUT DIAGRAM
TOP VIEW
V
DDQ
V
TT
GND
V
SENSE
1
2
3
4
8
7
6
5
TOP VIEW
V
CC
V
DDQ
SEL
V
REF
FSBSEL
V
DDQ
V
TT
GND
V
SENSE
1
2
3
4
8
7
GND
6
5
V
CC
V
DDQ
SEL
V
REF
FSBSEL
8-lead SOIC
Note: This drawing is not to scale.
8-lead PSOP
PIN DESCRIPTIONS
SOIC-8
LEAD(S)
1
2
3
4
5
6
7
8
NAME
V
DDQ
V
TT
GND
V
SENSE
FSBSEL
V
REF
V
DDQ
SEL
V
CC
DESCRIPTION
V
DDQ
Outputs either 1.225V/1.45V FSB or V
DDQ
/2 DDR (See note 1)
Ground
Feedback voltage input
Selects FSB output for either V
TT
=1.225V or 1.45V
1.25V reference voltage input for DDR bus
Select output to support FSB or DDR applications
Power for internal control circuits
Note 1: Assumes V
DDQ
and V
DDQ
SEL are tied together in DDR application.
Ordering Information
PART NUMBERING INFORMATION
Standard Finish
Ordering Part
Pins
8
8
Package
PSOP-8
SOIC-8
Number
1
CM3107-00SB
CM3107-00SN
Part Marking
CM3107-00SB
CM310701S
Lead-free Finish
Ordering Part
Number
1
CM3107-12SH
CM3107-00SM
Part Marking
CM3107-00SH
CM3107-00SM
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
02/02/04
CM3107
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
V
CC
Operating Supply Voltage
V
DDQ
Input Voltage
Pin Voltages
V
TT
Output
Any other pins
ESD (HBM)
Storage Temperature Range
Operating Temperature Range
Ambient
Junction
Power Dissipation (see note 1)
RATING
7
7
7
7
±2000
-40 to +150
-40 to +85
-40 to +150
Internally Limited
UNITS
V
V
V
V
V
°C
°C
°C
W
Note 1: These devices must be derated based on thermal resistance at elevated temperatures. The device packaged in a 8-lead
SOIC leadframe must be derated at
θ
JA
= 151
°C/W
.
θ
JA
of the 8-lead PSOP is 40
°C/W.
STANDARD OPERATING CONDITIONS
PARAMETER
V
DDQ
V
CC
Ambient Operating Temperature
CV
OUT
VALUE
2.5 to 3.3
2.5 to 3.3
0 to +70
220
±20%
UNITS
V
V
°C
µF
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
3
CM3107
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
V
IN
PARAMETER
Input Voltage Range
V
DDQ
V
CC
V
CC
Quiescent Current
Output Voltage
I
VTT
= 0A
I
VTT
= 0A, V
DDQ
= 2.5V,
V
DDQ
SEL= logic "1" = 2.5V
V
DDQ
SEL= logic "0", FSBSEL= logic "0"
V
DDQ
SEL = logic "0", FSBSEL = logic "1"
I
VTT
= 0A, V
DDQ
= 3.3V,
V
DDQ
SEL= logic "0", FSBSEL= logic "0"
V
DDQ
SEL = logic "0", FSBSEL = logic "1"
V
RLOAD
V
REF
VOS
VTT
Z
REF
Z
VDDQSEL
CL
VTT
V
FSBSEL
Load Regulation
Output Reference Voltage
Output Offset from V
REF
V
REF
Output Impedance
V
VDDQSEL
Input Impedance
V
TT
Current Limit
Output Selection Logic
(FSBSEL)
Logic "1" Level
Logic "0" Level
Shutdown Temperature
Thermal Hysteresis
1.5
0.4
150
50
-5µA < I
VREF
< 5µA
0A < I
VTT
< 2.0A or 0A < I
VTT
< -2.0A
V
DDQ
SEL = 2.5V, I
VREF
=0A
1.225
-20
5
100
2.5
1.225
1.200
1.425
CONDITIONS
MIN
2.2
2.2
TYP
2.5
2.5
450
1.250
1.225
1.450
1.275
1.250
1.475
MAX
V
CC
5.5
UNITS
V
V
µA
V
V
V
V
I
CC
V
TT
1.200
1.425
1.225
1.450
6.25
1.250
1.250
1.475
V
V
mV
1.275
20
V
mV
kΩ
kΩ
A
V
V
°C
°C
T
DISABLE
T
HYST
Note 1: Operating Characteristics are over Standard Operating Conditions unless otherwise specified.
© 2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
02/02/04
CM3107
Performance Information
Typical DC Characteristics (nominal conditions unless otherwise specified)
Figure 1. Output Voltage with
V
CC
Supply (V
DDQ
SEL= 2.5V)
Figure 3. Reference Voltage with
V
CC
Supply (V
DDQ
SEL= 2.5V)
Figure 2. Load Regulation (Sink)
Figure 4. Load Regulation (Source)
© 2004 California Micro Devices Corp. All rights reserved.
02/02/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
L
Tel: 408.263.3214
L
Fax: 408.263.7846
L
www.calmicro.com
5
传感器
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