74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
Rev. 04 — 2 June 2008
Product data sheet
1. General description
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on
the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock
transition for predictable operation.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing a damaging backflow current through the
device when it is powered down.
2. Features
I
Wide supply voltage range from 0.8 V to 3.6 V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low noise overshoot and undershoot < 10 % of V
CC
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
NXP Semiconductors
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP2G80DC
74AUP2G80GT
74AUP2G80GD
74AUP2G80GM
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
VSSOP8
XSON8
XSON8U
XQFN8U
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
×
1.95
×
0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3
×
2
×
0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
SOT902-1
Type number
4. Marking
Table 2.
Marking codes
Marking code
p80
p80
p80
p80
Type number
74AUP2G80DC
74AUP2G80GT
74AUP2G80GD
74AUP2G80GM
5. Functional diagram
1D
1Q
1CP
2D
2Q
2CP
001aah893
D
CP
D
CP
001aah894
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74AUP2G80_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2008
2 of 20
NXP Semiconductors
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
CP
C
C
C
C
D
TG
C
TG
C
Q
C
C
TG
TG
C
C
mna651
Fig 3.
Logic diagram (one flip-flop)
6. Pinning information
6.1 Pinning
74AUP2G80
1CP
1
8
V
CC
1D
2
7
1Q
74AUP2G80
2Q
1CP
1D
2Q
GND
1
2
3
4
001aaf308
3
6
2D
8
7
6
5
V
CC
1Q
2D
2CP
GND
4
5
2CP
001aaf309
Transparent top view
Fig 4.
Pin configuration SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT833-1 (XSON8)
74AUP2G80_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2008
3 of 20
NXP Semiconductors
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
74AUP2G80
terminal 1
index area
1Q
1
V
CC
8
74AUP2G80
1CP
1D
2Q
GND
1
2
3
4
8
7
6
5
V
CC
7
1CP
2D
1Q
2D
2CP
2CP
2
6
1D
3
4
5
2Q
GND
001aaf310
001aai216
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2 (XSON8U)
Fig 7.
Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT765-1, SOT833-1 and
SOT996-2
1CP, 2CP
1D, 2D
GND
1Q, 2Q
V
CC
1, 5
2, 6
4
7, 3
8
SOT902-1
7, 3
6, 2
4
1, 5
8
clock input
data input
ground (0 V)
data output
supply voltage
Description
7. Functional description
Table 4.
Input
nCP
↑
↑
L
[1]
H = HIGH voltage level;
L = LOW voltage level;
↑
= LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one setup time prior to the LOW-to-HIGH CP transition.
Function table
[1]
Output
nD
L
H
X
nQ
H
L
q
74AUP2G80_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2008
4 of 20
NXP Semiconductors
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
[1]
Max
+4.6
-
+4.6
±50
+4.6
±20
+50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
> V
CC
or V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
−50
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
−40
-
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
°C
ns/V
74AUP2G80_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2008
5 of 20
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