74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
Rev. 04 — 30 June 2009
Product data sheet
1. General description
The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The
3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE
causes the output to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
This device has the input-disable feature, which allows floating input signals. The inputs
are disabled when the output enable input nOE is HIGH.
2. Features
I
Wide supply voltage range from 0.8 V to 3.6 V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low-noise overshoot and undershoot < 10 % of V
CC
I
Input-disable feature allows floating input conditions
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
NXP Semiconductors
74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP2G240DC
74AUP2G240GT
74AUP2G240GD
74AUP2G240GM
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
VSSOP8
XSON8
XSON8U
XQFN8U
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1
×
1.95
×
0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3
×
2
×
0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
SOT902-1
Type number
4. Marking
Table 2.
Marking codes
Marking code
[1]
p40
p40
p40
p40
Type number
74AUP2G240DC
74AUP2G240GT
74AUP2G240GD
74AUP2G240GM
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
EN
1OE
1A
2OE
2A
2Y
1Y
EN
001aah782
001aah783
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74AUP2G240_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 30 June 2009
2 of 20
NXP Semiconductors
74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
74AUP2G240
1OE
1
8
V
CC
1A
2
7
2OE
74AUP2G240
2Y
1OE
1A
2Y
GND
1
2
3
4
001aaf407
3
6
1Y
8
7
6
5
V
CC
2OE
1Y
2A
GND
4
5
2A
001aaf408
Transparent top view
Fig 3.
Pin configuration SOT765-1 (VSSOP8)
Fig 4.
Pin configuration SOT833-1 (XSON8)
74AUP2G240
terminal 1
index area
2OE
1
V
CC
8
74AUP2G240
1OE
1A
2Y
GND
1
2
3
4
8
7
6
5
V
CC
7
1OE
1Y
2OE
1Y
2A
2A
2
6
1A
3
4
5
2Y
GND
001aaf409
001aaj919
Transparent top view
Transparent top view
Fig 5.
Pin configuration SOT996-2 (XSON8U)
Fig 6.
Pin configuration SOT902-1 (XQFN8U)
6.2 Pin description
Table 3.
Symbol
1OE, 2OE
1A, 2A
GND
1Y, 2Y
V
CC
Pin description
Pin
SOT765-1, SOT833-1 and SOT996-2
1, 7
2, 5
4
6, 3
8
SOT902-1
7, 1
6, 3
4
2, 5
8
output enable input (active LOW)
data input
ground (0 V)
data output
supply voltage
Description
74AUP2G240_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 30 June 2009
3 of 20
NXP Semiconductors
74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
7. Functional description
Table 4.
Input
nOE
L
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.
Function table
[1]
Output
nA
L
H
X
nY
H
L
Z
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
−50
[1]
Max
+4.6
-
+4.6
-
+4.6
±20
50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
−50
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly with 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 118
°C
the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
−40
0
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
°C
ns/V
74AUP2G240_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 30 June 2009
4 of 20
NXP Semiconductors
74AUP2G240
Low-power dual inverting buffer/line driver; 3-state
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
°C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−20 µA;
V
CC
= 0.8 V to 3.6 V
I
O
=
−1.1
mA; V
CC
= 1.1 V
I
O
=
−1.7
mA; V
CC
= 1.4 V
I
O
=
−1.9
mA; V
CC
= 1.65 V
I
O
=
−2.3
mA; V
CC
= 2.3 V
I
O
=
−3.1
mA; V
CC
= 2.3 V
I
O
=
−2.7
mA; V
CC
= 3.0 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
µA;
V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
I
I
OZ
I
OFF
∆I
OFF
I
CC
input leakage current
OFF-state output current
power-off leakage current
additional power-off
leakage current
supply current
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
V
I
= V
IH
or V
IL
; V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 3.6 V
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
V
I
or V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 0.2 V
V
I
= GND or V
CC
; I
O
= 0 A;
V
CC
= 0.8 V to 3.6 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.3
×
V
CC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.1
±0.2
±0.2
0.5
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
V
CC
−
0.1
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.75
×
V
CC
-
0.70
×
V
CC
-
0.65
×
V
CC
-
1.6
2.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
Conditions
Min
Typ
Max
Unit
0.30
×
V
CC
V
0.35
×
V
CC
V
0.7
0.9
V
V
74AUP2G240_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 30 June 2009
5 of 20
嵌入式系统
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