74AUP1G175
Low-power D-type flip-flop with reset; positive-edge trigger
Rev. 02 — 28 February 2008
Product data sheet
1. General description
The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type
flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q
output.The master reset (MR) is an asynchronous active LOW input and operates
independently of the clock input. Information on the data input is transferred to the
Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable
one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V. This device ensures a very low
static and dynamic power consumption across the entire V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
I
Wide supply voltage range from 0.8 V to 3.6 V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114E Class 3A exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD 78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low noise overshoot and undershoot < 10 % of V
CC
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
NXP Semiconductors
74AUP1G175
Low-power D-type flip-flop with reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP1G175GW
74AUP1G175GM
74AUP1G175GF
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SC-88
XSON6
XSON6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
×
1.45
×
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
×
1
×
0.5 mm
4. Marking
Table 2.
Marking
Marking code
aT
aT
aT
Type number
74AUP1G175GW
74AUP1G175GM
74AUP1G175GF
5. Functional diagram
6
3
MR
D
FF
Q
4
CP
001aaa468
1
3
6
CP
D
MR
001aaa469
1
Q
4
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
CP
C
C
C
C
Q
C
D
C
MR
C
C
C
C
001aaa466
Fig 3.
Logic diagram
74AUP1G175_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 28 February 2008
2 of 20
NXP Semiconductors
74AUP1G175
Low-power D-type flip-flop with reset; positive-edge trigger
6. Pinning information
6.1 Pinning
74AUP1G175
74AUP1G175
CP
CP
1
6
MR
GND
GND
2
5
V
CC
D
D
3
001aaa467
1
6
MR
CP
GND
74AUP1G175
1
2
3
6
5
4
MR
V
CC
Q
2
5
V
CC
3
4
Q
D
4
Q
001aab657
001aae246
Transparent top view
Transparent top view
Fig 4.
Pin configuration SOT363
(SC-88)
Fig 5.
Pin configuration SOT886
(XSON6)
Fig 6.
Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Symbol
CP
GND
D
Q
V
CC
MR
Pin description
Pin
1
2
3
4
5
6
Description
clock input (LOW-to-HIGH, edge-triggered)
ground (0 V)
data input
flip-flop output
supply voltage
master reset input (active LOW)
7. Functional description
Table 4.
Function table
[1]
Input
MR
Reset (clear)
Load ‘1’
Load ‘0’
[1]
Operating mode
Output
CP
X
↑
↑
D
X
h
l
Q
L
H
L
L
H
H
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑
= LOW-to-HIGH CP transition;
X = don’t care.
74AUP1G175_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 28 February 2008
3 of 20
NXP Semiconductors
74AUP1G175
Low-power D-type flip-flop with reset; positive-edge trigger
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
-
[1]
Max
+4.6
-
+4.6
±50
+4.6
±20
50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
output clamping current V
O
> V
CC
or V
O
< 0 V
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
−40 °C
to +125
°C
[2]
Active mode and Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
−50
−65
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SC-88 packages: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 45
°C
the value of P
tot
derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
−40
-
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
°C
ns/V
74AUP1G175_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 28 February 2008
4 of 20
NXP Semiconductors
74AUP1G175
Low-power D-type flip-flop with reset; positive-edge trigger
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
°C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−20 µA;
V
CC
= 0.8 V to 3.6 V
I
O
=
−1.1
mA; V
CC
= 1.1 V
I
O
=
−1.7
mA; V
CC
= 1.4 V
I
O
=
−1.9
mA; V
CC
= 1.65 V
I
O
=
−2.3
mA; V
CC
= 2.3 V
I
O
=
−3.1
mA; V
CC
= 2.3 V
I
O
=
−2.7
mA; V
CC
= 3.0 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
µA;
V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
I
I
OFF
∆I
OFF
I
CC
∆I
CC
C
I
C
O
input leakage current
power-off leakage current
additional power-off
leakage current
supply current
additional supply current
input capacitance
output capacitance
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
V
I
or V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 0.2 V
V
I
= GND or V
CC
; I
O
= 0 A;
V
CC
= 0.8 V to 3.6 V
V
I
= V
CC
−
0.6 V; I
O
= 0 A;
V
CC
= 3.3 V
V
CC
= 0 V to 3.6 V; V
I
= GND or V
CC
V
O
= GND; V
CC
= 0 V
[1]
Conditions
Min
Typ
Max
-
-
-
-
Unit
V
V
V
V
0.70
×
V
CC
-
0.65
×
V
CC
-
1.6
2.0
-
-
-
-
V
CC
−
0.1
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
1.7
0.30
×
V
CC
V
0.35
×
V
CC
V
0.7
0.9
-
-
-
-
-
-
-
-
0.1
0.3
×
V
CC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
0.5
40
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
pF
pF
0.75
×
V
CC
-
74AUP1G175_2
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 28 February 2008
5 of 20
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