74AHC1G09
2-input AND gate with open-drain output
Rev. 02 — 18 December 2007
Product data sheet
1. General description
The 74AHC1G09 is a high-speed Si-gate CMOS device.
The 74AHC1G09 provides the 2-input AND function with open-drain output.
The output of the 74AHC1G09 is an open drain and can be connected to other open-drain
outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. For
digital operation this device must have a pull-up resistor to establish a logic HIGH level.
2. Features
s
s
s
s
High noise immunity
Low power dissipation
SOT353-1 and SOT753 package options
ESD protection:
x
HBM JESD22-A114E: exceeds 2000 V
x
MM JESD22-A115-A: exceeds 200 V
x
CDM JESD22-C101C: exceeds 1000 V
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C.
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC1G09GW
74AHC1G09GV
−40 °C
to +125
°C
−40 °C
to +125
°C
TSSOP5
SC-74A
Description
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
plastic surface-mounted package; 5 leads
Version
SOT353-1
SOT753
Type number
4. Marking
Table 2.
Marking
Marking code
A9
A09
Type number
74AHC1G09GW
74AHC1G09GV
NXP Semiconductors
74AHC1G09
2-input AND gate with open-drain output
5. Functional diagram
Y
A
B
A
1
2
4
Y
1
2
001aad598
&
4
B
GND
001aad600
001aad599
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
B
A
1
2
5
V
CC
09
4
001aad601
GND
3
Y
Fig 4. Pin configuration SOT353-1 (TSSOP5) and SOT753 (SC-74A)
6.2 Pin description
Table 3.
Symbol
B
A
GND
Y
V
CC
Pin description
Pin
1
2
3
4
5
Description
data input B
data input A
ground (0 V)
data output Y
supply voltage
7. Functional description
Table 4.
Input
A
L
L
H
H
[1]
Function table
[1]
Output
B
L
H
L
H
Y
L
L
L
Z
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
74AHC1G09_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 December 2007
2 of 10
NXP Semiconductors
74AHC1G09
2-input AND gate with open-drain output
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
GND current
storage temperature
total power dissipation
Conditions
[1]
Min
−0.5
−0.5
−0.5
−0.5
-
-
-
-
-
−65
Max
+7.0
+7.0
+7.0
+7.0
−20
±20
25
±75
±75
+150
250
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
mW
active mode
high-impedance mode
V
I
<
−0.5
V
V
O
<
−0.5
V
V
O
>
−0.5
V
[1]
[1]
[1]
[1]
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP5 and SC-74A packages: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Recommended operating operations
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
active mode
high-impedance mode
Conditions
Min
2.0
0
0
0
−40
-
-
Typ
5.0
-
-
-
+25
-
-
Max
5.5
5.5
V
CC
6.0
+125
100
20
Unit
V
V
V
V
°C
ns/V
ns/V
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
Min
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
74AHC1G09_2
25
°C
Typ
-
-
-
-
-
-
Max
-
-
-
0.5
0.9
1.65
1.5
2.1
3.85
-
-
-
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
1.5
2.1
3.85
-
-
-
Max
-
-
-
0.5
0.9
1.65
Min
1.5
2.1
3.85
-
-
-
Max
-
-
-
0.5
0.9
1.65
V
V
V
V
V
V
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 December 2007
3 of 10
NXP Semiconductors
74AHC1G09
2-input AND gate with open-drain output
Table 7.
Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
OL
Conditions
Min
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
µA;
V
CC
= 2.0 V
I
O
= 50
µA;
V
CC
= 3.0 V
I
O
= 50
µA;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
OZ
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
-
-
-
-
-
-
-
-
-
25
°C
Typ
0
0
0
-
-
-
-
-
1.5
Max
0.1
0.1
0.1
0.36
0.36
±0.1
±0.25
1.0
10
-
-
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
-
-
-
-
-
-
Max
0.1
0.1
0.1
0.44
0.44
±1.0
±2.5
10
10
-
-
Min
-
-
-
-
-
-
Max
0.1
0.1
0.1
0.55
0.55
±2.0
±10.0
20
10
V
V
V
V
V
µA
µA
µA
pF
OFF-state
V
I
= V
IH
or V
IL
; V
O
= V
CC
or
output current GND; V
CC
= 5.5 V
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; for test circuit see
Figure 6.
Symbol Parameter
t
pd
Conditions
Min
propagation delay A and B to Y;
see
Figure 5
V
CC
= 3.0 V to 3.6 V
C
L
= 15 pF
C
L
= 50 pF
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
C
PD
power dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz;
V
I
= GND to V
CC
[4]
[3]
[1]
25
°C
Typ Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
[2]
-
-
-
-
-
4.6
6.5
3.2
4.6
5
7.5
11.0
5.5
7.5
-
1.0
1.5
1.0
1.5
-
8.5
12.0
6.5
8.0
-
1.0
1.5
1.0
1.5
-
9.0
12.5
7.0
8.5
-
ns
ns
ns
ns
pF
[1]
[2]
[3]
[4]
t
pd
is the same as t
PZL
and t
PLZ
.
Typical values are measured at V
CC
= 3.3 V.
Typical values are measured at V
CC
= 5.0 V.
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N + (C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
×
V
CC2
×
f
o
) = dissipation due to the output if the combination of the pull up voltage and resistance results in V
CC
at the output.
74AHC1G09_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 December 2007
4 of 10
NXP Semiconductors
74AHC1G09
2-input AND gate with open-drain output
12. Waveforms
V
I
A, B input
GND
t
PLZ
V
CC
Y output
V
OL
V
X
001aad602
V
M
t
PZL
V
M
Measurement points are given in
Table 9.
V
OL
is the typical voltage output level that occur with the output load.
Fig 5. The data input (A, B) to output (Y) propagation delays
Table 9.
Input
V
M
0.5V
CC
Measurement points
Output
V
M
0.5V
CC
V
X
V
OL
+ 0.3 V
S1
V
CC
PULSE
GENERATOR
V
I
D.U.T.
RT
CL
V
O
RL =
1000
Ω
V
CC
open
GND
mna232
Test data is given in
Table 10.
Definitions for test circuit:
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
Fig 6. Load circuit for switching times
Table 10.
Input
V
I
GND to V
CC
GND to V
CC
t
r
, t
f
≤
3.0 ns
≤
3.0 ns
Test data
Load
R
L
1000
Ω
1000
Ω
C
L
15 pF
50 pF
S
1
t
PHZ
, t
PZH
GND
GND
t
PLZ
, t
PZL
V
CC
V
CC
t
PLH
, t
PHL
open
open
74AHC1G09_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 18 December 2007
5 of 10
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
