CAT34C02
FEATURES
2-Kb I
2
C EEPROM for DDR2 DIMM Serial Presence Detect
DEVICE DESCRIPTION
The CAT34C02 is a 2-Kb Serial CMOS EEPROM,
internally organized as 16 pages of 16 bytes each, for
a total of 256 bytes of 8 bits each.
It features a 16-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I
2
C protocol.
Write operations can be inhibited by taking the WP pin
High (this protects the entire memory) or by setting an
internal Write Protect flag via Software command (this
protects the lower half of the memory).
In addition to Permanent Software Write Protection,
the CAT34C02 also features JEDEC compatible
Reversible Software Write Protection for DDR2 Serial
Presence Detect (SPD) applications operating over
the 1.7 V to 3.6 V supply voltage range.
The CAT34C02 is fully backwards compatible with
earlier DDR1 SPD applications operating over the
1.7 V to 5.5 V supply voltage range.
■
Supports Standard and Fast I
2
C Protocol
■
1.7 V to 5.5 V Supply Voltage Range
■
16-Byte Page Write Buffer
■
Hardware Write Protection for entire memory
■
Software Write Protection for lower 128 Bytes
■
Schmitt Triggers and Noise Suppression Filters
on I
2
C Bus Inputs (SCL and SDA).
■
Low power CMOS technology
■
1,000,000 program/erase cycles
■
100 year data retention
■
RoHS-compliant packages
■
Industrial temperature range
For Ordering Information details, see page 14.
PIN CONFIGURATION
TSSOP (Y)
TDFN (VP2)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
FUNCTIONAL SYMBOL
VCC
For the location of Pin 1, please consult the
corresponding package drawing.
SCL
A 2, A 1 , A 0
WP
CAT34C02
SDA
PIN FUNCTIONS
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
VSS
* Catalyst carries the I
2
C protocol under a license from the Philips Corporation.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1095, Rev. H
CAT34C02
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
Voltage on Any Pin with Respect to Ground
(1)
-65°C to +150°C
-0.5 V to +6.5 V
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
(2)
Symbol
N
END
(*)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
(*) Page Mode, V
CC
= 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.7 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
I
CC
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Parameter
Supply Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
> 2.5 V, I
OL
= 3.0 mA
V
CC
> 1.7 V, I
OL
= 1.0 mA
Test Conditions
Read or Write at 400 kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
-0.5
Min
Max
1
2
2
V
CC
x 0.3
Units
mA
μA
μA
V
V
V
V
V
CC
x 0.7 V
CC
+ 0.5
0.4
0.2
PIN IMPEDANCE CHARACTERISTICS
T
A
= 25°C, f = 400 kHz, V
CC
= 5 V
Symbol
C
IN(2)
C
IN(2)
Z
WPL
I
LWPH
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Low Impedance
WP Input High Leakage
Conditions
V
IN
= 0 V
V
IN
= 0 V
V
IN
< 0.5 V
V
IN
> V
CC
x 0.7
Min
Max
8
6
Units
pF
pF
kΩ
μA
5
70
2
Doc. No. 1095, Rev. H
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT34C02
A.C. CHARACTERISTICS
(1)
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C.
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F(2)
t
SU:STO
t
BUF
t
AA
t
DH
T
i(2)
t
SU:WP
t
HD:WP
t
WR
t
PU(2, 3)
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this paramete.
(3) t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Fast
Min
0.6
1.3
0.6
0.6
0
100
Max
400
Units
kHz
μs
μs
μs
μs
μs
ns
300
300
0.6
1.3
ns
ns
μs
μs
0.9
100
100
0
2.5
μs
ns
ns
μs
μs
5
1
ms
ms
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data Hold Time
Data Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to SDA Data Out
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
Min
4
4.7
4
4.7
0
250
Max
100
1000
300
4
4.7
3.5
100
100
0
2.5
5
1
A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2V
CC
to 0.8V
CC
< = 50 ns
0.3V
CC
, 0.7V
CC
0.5V
CC
Current Source: I
OL
= 3mA; C
L
= 100pF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1095, Rev. H
CAT34C02
POWER-ON RESET (POR)
The CAT34C02 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
The CAT34C02 will power up into Standby mode after
V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
I
2
C BUS PROTOCOL
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake-up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when follow-
ing a Write command) or sends the Slave into standby
mode (when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address are set to 1010, for normal Read/Write opera-
tions (Figure 2). The next 3 bits, A
2
, A
1
and A
0
, select
one of 8 possible Slave devices. The last bit, R/W,
specifies whether a Read (1) or Write (0) operation is
to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
th
clock cycle (Figure 3). The Slave will
also acknowledge the byte address and every data
byte presented in Write mode. In Read mode the Slave
shifts out a data byte, and then releases the SDA line
during the 9
th
clock cycle. If the Master acknowledges
the data, then the Slave continues transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by sending a STOP to
the Slave. Bus timing is illustrated in Figure 4.
PIN DESCRIPTION
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A
0
, A
1
and A
2
:
The Address pins accept the device ad-
dress. These pins have on-chip pull-down resistors.
WP:
The Write Protect input pin inhibits all write op-
erations, when pulled HIGH. This pin has an on-chip
pull-down resistor.
FUNCTIONAL DESCRIPTION
The CAT34C02 supports the Inter-Integrated Circuit (I
2
C)
Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by
a Master device, which generates the serial clock and
all START and STOP conditions. The CAT34C02 acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected
to the bus as determined by the device address inputs
A
0
, A
1
, and A
2
.
Doc. No. 1095, Rev. H
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT34C02
Figure 1. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 2. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
Figure 3. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 4. Bus Timing
tF
tLOW
tHIGH
tLOW
tR
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1095, Rev. H
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