74ABT652A
Octal transceiver/register; non-inverting; 3-state
Rev. 02 — 12 March 2010
Product data sheet
1. General description
The 74ABT652A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT652A transceiver/register consists of bus transceiver circuits with 3-state
outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of
data directly from the input bus or the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin (CPAB or CPBA) goes HIGH.
Output Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for bus
management.
2. Features and benefits
I
I
I
I
I
I
I
I
I
Independent registers for A and B buses
Multiplexed real-time and stored data
3-state outputs
Live insertion/extraction permitted
Power-up 3-state
Power-up reset
Output capability: +64 mA to
−32
mA
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
N
HBM JESD22-A114F exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ABT652AD
−40 °C
to +85
°C
SO24
SSOP24
TSSOP24
Description
plastic small outline package; 24 leads; body width
7.5 mm
Version
SOT137-1
Type number
74ABT652ADB
−40 °C
to +85
°C
74ABT652APW
−40 °C
to +85
°C
plastic shrink small outline package; 24 leads; body width SOT340-1
5.3 mm
plastic thin shrink small outline package; 24 leads; body
width 4.4 mm
SOT355-1
NXP Semiconductors
74ABT652A
Octal transceiver/register; non-inverting; 3-state
4. Block diagram
21
3
23
22
1
2
EN1[BA]
EN2[AB]
C4
G5
C6
G7
≥1
7
7
5
5
≥1
1
2
19
18
17
16
15
14
13
001aae846
4
4
5
6
7
8
9
10 11
5
6
3
21
7
8
9
10
11
20 19 18 17 16 15 14 13
001aae845
1
6D
1
4D
20
23
22
2
1
A0 A1 A2 A3 A4 A5 A6 A7
CPBA
SBA
SAB
CPAB
B0 B1 B2 B3 B4 B5 B6 B7
OEAB
OEBA
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74ABT652A_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 12 March 2010
2 of 19
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
74ABT652A_2
Product data sheet
REAL TIME BUS TRANSFER
BUS A TO BUS B
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A OR B
A
B
A
B
A
B
OEAB OEBA CPAB CPBA
H
H
X
X
SAB
L
SBA
X
OEAB OEBA CPAB CPBA
H
X
X
X
X
L
H
L
SAB
X
X
X
SBA
X
X
X
OEAB OEBA CPAB CPBA
H
L
H/L
H/L
SAB
H
SBA
H
001aae847
NXP Semiconductors
REAL TIME BUS TRANSFER
BUS B TO BUS A
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 12 March 2010
A
B
OEAB OEBA CPAB CPBA
X
L
L
X
SAB
X
SBA
L
© NXP B.V. 2010. All rights reserved.
74ABT652A
Octal transceiver/register; non-inverting; 3-state
3 of 19
Fig 3. Real time bus transfer and storage
NXP Semiconductors
74ABT652A
Octal transceiver/register; non-inverting; 3-state
OEBA
21
OEAB
3
CPBA
SBA
CPAB
SAB
23
22
1
2
1 of 8 channels
1D
C1
Q
A0
4
1D
C1
Q
20
B0
A1
A2
A3
A4
A5
A6
A7
5
6
7
8
9
10
11
DETAIL A
×
7
19
18
17
16
15
14
13
001aae848
B1
B2
B3
B4
B5
B6
B7
Fig 4. Logic diagram
74ABT652A_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 12 March 2010
4 of 19
NXP Semiconductors
74ABT652A
Octal transceiver/register; non-inverting; 3-state
5. Pinning information
5.1 Pinning
74ABT652A
CPAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
1
2
3
4
5
6
7
8
9
24 V
CC
23 CPBA
22 SBA
21 OEBA
20 B0
19 B1
18 B2
17 B3
16 B4
15 B5
14 B6
13 B7
001aae844
A6 10
A7 11
GND 12
Fig 5. Pin configuration
5.2 Pin description
Table 2.
Symbol
CPAB
SAB
OEAB
A0, A1, A2, A3, A4, A5, A6, A7
GND
B0, B1, B2, B3, B4, B5, B6, B7
OEBA
SBA
CPBA
V
CC
Pin description
Pin
1
2
3
4, 5, 6, 7, 8, 9, 10, 11
12
20, 19, 18, 17, 16, 15, 14, 13
21
22
23
24
Description
A to B clock input
A to B select input
A to B output enable input
data input/output (A side)
ground (0 V)
data input/output (B side)
B to A output enable input (active LOW)
B to A select input
B to A clock input
positive supply voltage
74ABT652A_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 12 March 2010
5 of 19
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
