IDT74ALVC125
3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
QUADRUPLE BUS
BUFFER GATE WITH
3-STATE OUTPUTS
FEATURES:
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V ± 0.2V
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP and TSSOP packages
IDT74ALVC125
DESCRIPTION:
This quadruple bus buffer gate is built using advanced dual metal CMOS
technology. The ALVC125 features independent line drivers with 3-state
outputs. Each output is disabled when the associated output-enable (OE)
input is high.
The ALVC125 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Drive Features for ALVC125:
– High Output Drivers: ±24mA
– Suitable for heavy loads
APPLICATIONS:
•
3.3V High Speed Systems
•
3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
3
OE
10
1
A
2
3
1
Y
3
A
9
8
3
Y
2
OE
4
4
OE
13
2
A
5
6
2
Y
4
A
12
11
4
Y
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-4635/-
IDT74ALVC125
3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
>
V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
ALVC QUAD Link
Max.
– 0.5 to + 4.6
– 0.5 to V
CC
+ 0.5
– 65 to + 150
– 50 to + 50
± 50
– 50
±100
Unit
V
V
°C
mA
mA
mA
mA
1
OE
1
A
1
Y
2
OE
2
A
2
Y
1
2
3
4
5
6
7
14
13
12
SO14-1
SO14-2
11
SO14-3
10
9
8
V
CC
4
OE
4
A
4
Y
3
OE
3
A
3
Y
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GN D
SOIC/ SSOP/ TSSOP
TOP VIEW
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
CAPACITANCE
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
(TA = +25°C, f = 1.0MHz)
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
7
9
9
Unit
pF
pF
pF
ALVC QUAD Link
I/O Port Capacitance
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
xOE
xA
xY
Description
Output Enable Inputs (Active LOW)
Data Inputs
3-State Outputs
FUNCTION TABLE
Inputs
xOE
L
L
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
(each buffer)
(1)
xA
H
L
X
Output
xY
H
L
Z
2
IDT74ALVC125
3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
=
−40°C
to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
V
H
I
CCL
I
CCH
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
Quiescent Power Supply
Current Variation
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
−
0.6V,
other inputs at V
CC
or GND
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Min.
1.7
2
—
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
– 0.7
100
0.1
—
Max.
—
—
0.7
0.8
±5
±5
± 10
± 10
– 1.2
—
10
750
µA
µA
V
mV
µA
µA
µA
V
Unit
V
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
ALVC QUAD Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to + 85°C.
c
3
IDT74ALVC125
3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, T
A
= 25
o
C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per gate Outputs enabled
Power Dissipation Capacitance per gate Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
20
3
V
CC
= 3.3V ± 0.3V
Typical
30
6
Unit
pF
pF
SWITCHING CHARACTERISTICS
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
xA to xY
Output Enable Time
xOE to xY
Output Disable Time
xOE to xY
(1)
V
CC
= 2.5V ± 0.2V
Min.
1
1.5
1
Max.
3.1
5.4
4.1
V
CC
= 2.7V
Min.
1
1.5
1.3
Max.
3.1
5.3
4.4
V
CC
= 3.3V ± 0.3V
Min.
1.1
1.5
1.7
Max.
3
4.5
4.2
Unit
ns
ns
ns
NOTE:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
4
IDT74ALVC125
3.3V CMOS QUADRUPLE BUS BUFFER GATE
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V ± 0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V ± 0.2V Unit
2 x Vcc
V
Vcc
Vcc / 2
150
150
30
V
V
mV
mV
pF
ALVC QUAD Link
SAM E PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
ALV C Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
Generator
(1, 2)
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORMALLY
CLO SED
LOW
t
PZH
OUTPUT
SW ITCH
NORMALLY
OPEN
HIGH
V
LO AD/2
V
T
t
PH Z
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LO AD/2
V
LZ
V
OL
V
OH
V
HZ
0V
V
LO AD
Open
GND
V
IN
D.U.T.
V
OUT
R
T
500
Ω
C
L
ALVC Link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
TIM ING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
R EM
t
S U
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
ALV C Link
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
GND
Open
ALVC QUAD Link
t
S U
t
H
OUTPUT SKEW -
TSK
(x)
INPUT
t
PLH1
t
PH L1
V
IH
V
T
0V
V
OH
PULSE WIDTH
LOW -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
ALV C Link
OUTPUT 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
OUTPUT 2
t
PLH2
t
PH L2
V
T
V
OL
t
SK
(x)
= t
PL H2
-
t
P LH 1
or
t
PH L2
-
t
P HL1
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
ALVC Link
5
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