Integrated
Circuit
Systems, Inc.
ICS9148-20
Pentium/Pro
TM
System Clock Chip
General Description
The
ICS9148-20
is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
Features include four CPU and eight PCI clocks. Three
reference outputs are available equal to the crystal frequency.
Additionally, the device meets the Pentium power-up
stabilization requirement, assuring that CPU and PCI clocks
are stable within 2ms after power-up.
PD# pin enables low power mode by stopping crystal OSC
and PLL stages. Other power management features include
CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#,
which stops PCICLK (0:6) clocks.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining 50±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates.
The
ICS9148-20
accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Features
Generates system clocks for CPU, IOAPIC, PCI, plus
14.314 MHz REF (0:2), USB, and Super I/O
Supports single or dual processor systems
Supports Spread Spectrum modulation for CPU & PCI
clocks, down spread -0.5%
Skew from CPU (earlier) to PCI clock (rising edges for
100/33.3MHz) 1.5 to 4ns
Two fixed outputs at 48MHz.
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V output: CPU, IOAPIC
3.3V outputs: PCI, REF, 48MHz
No power supply sequence requirements
Uses external 14.318MHz crystal, no external load cap
required for C
L
=18pF crystal
48 pin 300 mil SSOP
Block Diagram
Pin Configuration
48-Pin SSOP
Power Groups
VDD = Supply for PLL core
VDD1 = REF (0:2), X1, X2
VDD2 = PCICLK_F, PCICLK (0:6)
VDD3 = 48MHz0, 48MHz1
VDDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:3)
9148-20 Rev C 03/28/98
Ground Groups
GND = Ground for PLL core
GND1 = REF (0:2), X1, X2
GND2 = PCICLK_F, PCICLK (0:6)
GND3 = 48MHz0, 48MHz1
GNDL1 = IOAPIC (0:1)
GNDL2 = CPUCLK (0:3)
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9148-20
Pin Descriptions
P IN N U M B E R
1, 2, 47
3
4
5
6, 12, 18
7
8, 10, 11, 13, 14, 16,
17
9, 15
19, 33
20, 32
21
22, 23
24
25
26, 27
28
29
30
31
37, 41
34, 38
35, 36, 39, 40
42
43
44, 45
46
48
P IN N A M E
R E F (0:2)
GND1
X1
X2
GND2
P C IC L K _F
P C IC L K (0:6)
VDD2
VDD
GND
VDD3
48M H z (0:1)
GND3
SE L 100/66.6#
FS (0:1)
SPREA D #
PD #
C P U _S T O P #
P C I_S TO P #
VDDL2
GNDL2
C P U C L K (3:0)
N /C
GNDL1
IOA P IC (0:1)
VDDL1
VDD1
T Y PE
OUT
PW R
IN
OUT
PW R
OUT
OUT
PW R
PW R
PW R
PW R
OUT
PW R
IN
IN
IN
IN
IN
IN
PW R
PW R
OUT
-
PW R
OUT
PW R
PW R
D E S C R IP T IO N
14.318M H z clock output
G round for R E F outputs
X TA L _IN 14.318M H z C rystal input, has internal 33pF
load cap and feed back resistor from X 2
X TA L _O U T C rystal output, has internal load cap 33pF
G round for P C I outputs
Free R unning PC I output
P C I clock outputs. T T L com patible 3.3V
Pow er for P C IC L K outputs, nom inally 3.3V
Isolated pow er for core, nom inally 3.3V
Isolated ground for core
P ow er for 48M H z outputs, nom inally 3.3V
48M H z outputs
G round for 48M H z outputs
Select pin for enabling 100M H z or 66.6M H z
H = 100M H z, L = 66.6M H z (P C I alw ays synchronous
33.3M H z)
F requency S elect pins
E nables S pread S pectrum feature w hen L OW
P ow ers dow n chip, active low
H alts C P U clocks at logic "0" level w hen low
H alts P C I B us at logic "0" level w hen low
P ow er for C P U outputs, nom inally 2.5V
G round for C P U outputs.
C P U and H ost clock outputs @ 2.5V
N ot internally connected
G round for IOA P IC outputs
IOA P IC outputs (14.318M H z) @ 2.5V
P ow er for IOA P IC outputs, nom inally 2.5V
S upply for R E F (0:1), X 1, X 2, nom inal 3.3V
Select Functions
Functionality
Tristate
Testmode
Spread Spectrum
CPU
HI - Z
TCLK/2
1
Modulated
2
PCI,
PCI_F
HI - Z
TCLK/6
1
Modulated
2
REF
HI - Z
TCLK
1
14.318MHz
IOAPIC
HI - Z
TCLK
1
14.318MHz
48 MHz
Selection
HI - Z
TCLK/2
1
48.0MHz
SEL 100/66#
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
Function
Tri-State
(Reserved)
(Reserved)
Active 66.6MHz CPU, 33.3 PCI
Test Mode
(Reserved)
(Reserved)
Active 100MHz CPU, 33.3 PCI
Notes:
1. TCLK is a test clock driven on the X1 (crystal in
pin) input during test mode.
2. -0.5% modulation down spread from the selected
frequency.
2
ICS9148-20
Technical Pin Function Descriptions
VDD(1,2,3)
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:2),
PCICLK_F, PCICLK (0:6), 48MHz0, 48MHz1.
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
VDDL1,2
This is the power supply for the CPUCLK (0:3) and IOAPIC
output buffers. The voltage level for these outputs may be
2.5 or 3.3volts. Clocks from the buffers that each supplies will
have a voltage swing from Ground to this level. For the actual
Guaranteed high and low voltage levels of these Clocks,
please consult the DC parameter table in this Data Sheet.
GND (1,2,3)
This is the ground to the internal core logic of the device as
well as the clock output buffers for REF(0:2), PCICLK_F,
PCICLK (0:6), 48MHz 0, 48MHz1.
GNDL (1,2)
This is the ground for the CPUCLK (0:3) and IOAPIC output
buffers.
X1
This input pin serves one of two functions. When the device
is used with a Crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal. When
the device is driven by an external clock signal, X1 is the
device input pin for that reference clock. This pin also
implements an internal Crystal loading capacitor that is
connected to ground. With a nominal value of 33pF no
external load cap is needed for a C
L
=17 to 18pF crystal.
X2
This Output pin is used only when the device uses a Crystal
as the reference frequency source. In this mode of operation,
X2 is an output signal that drives (or excites) the discrete
Crystal. The X2 pin will also implement an internal Crystal
loading capacitor nominally 33pF.
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive processor
and other CPU related circuitry that requires clocks which are
in tight skew tolerance with the CPU clock. The voltage
swing of these Clocks is controlled by the Voltage level
applied to the VDDL2 pin of the device. See the Functionality
Table for a list of the specific frequencies that are available
for these Clocks and the selection codes to produce them.
48MHz (0:1)
This is a fixed frequency Clock output that is typically used
to drive Super I/O devices. Outputs 0 and 1 are defined as
48MHz.
IOAPIC (0:1)
This Output is a fixed frequency Output Clock that runs at
the Reference Input (typically 14.31818MHz) . Its voltage
level swing is controlled by VDDL1 and may operate at 2.5 or
3.3volts.
REF(0:2)
The REF Outputs are fixed frequency Clocks that run at the
same frequency as the Input Reference Clock X1 or the
Crystal (typically 14.31818MHz) attached across X1 and X2.
PCICLK_F
This Output is equal to PCICLK(0:6) and is FREE RUNNING,
and will not be stopped by PCI_STOP#.
PCICLK (0:6)
These Output Clocks generate all the PCI timing requirements
for a Pentium/Pro based system. They conform to the current
PCI specification. They run at 33.3 MHz.
SELECT 100/66.6MHz#
This Input pin controls the frequency of the Clocks at the
CPUCLK, PCICLK and SDRAM output pins. If a logic 1
value is present on this pin, the 100MHz Clock will be selected.
If a logic 0 is used, the 66.6MHz frequency will be selected.
The PCI clock is multiplexed to be 33.3MHz for both select
cases. PCI is synchronous at the rising edge of PCI to the
CPU rising edge (with the skew making CPU early).
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms.
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLKs will have a turn ON
latency of at least 3 CPU clocks.
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not affect
PCICLK_F nor any other outputs.
3
ICS9148-20
Power Management
Clock Enable Configuration
Other Clocks,
REF,
IOAPICs,
48 MHz 0
48 MHz 1
Stopped
Running
Running
Running
Running
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
PCICLK
Crystal
VCOs
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
100/66.6MHz
100/66.6MHz
Low
Low
33.3 MHz
Low
33.3 MHz
Off
Running
Running
Running
Running
Off
Running
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than that of the
running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network
charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9148-20 Power Management Requirements
SIGNAL
SIGNAL STATE
Latency
No. of rising edges of free
running PCICLK
1
1
1
1
3ms
2max
CPU_ STOP#
PCI_STOP#
PD#
0 (Disabled)
2
1 (Enabled)
1
0 (Disabled)
2
1 (Enabled)
1
1 (Normal Operation)
3
0 (Power Down)
4
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF and IOAPIC will be stopped independent of these.
4
ICS9148-20
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the
ICS9148-20.
The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the
ICS9148-20.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the
ICS9148-20.
It is used to turn off the PCICLK (0:6) clocks for low power operation.
PCI_STOP# is synchronized by the
ICS9148-20
internally. The minimum that the PCICLK (0:6) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:6) clocks. PCICLK (0:6) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:6) clock on latency cycles are only one rising PCICLK. Clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148-20.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
5
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