UNISONIC TECHNOLOGIES CO., LTD
MJE13003
NPN SILICON POWER
TRANSISTORS
DESCRIPTION
These devices are designed for high–voltage, high–speed
power switching inductive circuits where fall time is critical. They
are particularly suited for 115 and 220V SWITCHMODE.
NPN SILICON TRANSISTOR
FEATURES
* Reverse biased SOA with inductive load @ Tc=100°C
* Inductive switching matrix 0.5 ~ 1.5 Amp, 25 and 100°C
Typical tc = 290ns @ 1A, 100°C.
* 700V blocking capability
APPLICATIONS
* Switching regulator’s, inverters
* Motor controls
* Solenoid/relay drivers
* Deflection circuits
Lead-free: MJE13003L
Halogen-free: MJE13003G
ORDERING INFORMATION
Normal
MJE13003-x-T60-A-K
MJE13003-x-T60-F-K
MJE13003-x-T6C-A-K
MJE13003-x-T6C-F-K
MJE13003-x-T92-A-B
MJE13003-x-T92-A -K
MJE13003-x-TA3-A-T
MJE13003-x-TM3-A-T
MJE13003-x-TN3-A-R
MJE13003-x-TN3-A-T
Ordering Number
Lead Free Plating
MJE13003L-x-T60-A-K
MJE13003L-x-T60-F-K
MJE13003L-x-T6C-A-K
MJE13003L-x-T6C-F-K
MJE13003L-x-T92-A-B
MJE13003L-x-T92-A-K
MJE13003L-x-TA3-A-T
MJE13003L-x-TM3-A-T
MJE13003L-x-TN3-A-R
MJE13003L-x-TN3-A-T
Pin Assignment
Packing
Halogen-Free
1
2
3
MJE13003G-x-T60-A-K TO-126
E
C
B
Bulk
MJE13003G-x-T60-F-K TO-126
B
C
E
Bulk
MJE13003G-x-T6C-A-K TO-126C E
C
B
Bulk
MJE13003G-x-T6C-F-K TO-126C B
C
E
Bulk
MJE13003G-x-T92-A-B TO-92
E
C
B Tape Box
MJE13003G-x-T92-A-K TO-92
E
C
B
Bulk
MJE13003G-x-TA3-A-T TO-220
B
C
E
Tube
MJE13003G-x-TM3-A-T TO-251
B
C
E
Tube
MJE13003G-x-TN3-A-R TO-252
B
C
E Tape Reel
MJE13003G-x-TN3-A-T TO-252
B
C
E
Tube
Package
www.unisonic.com.tw
Copyright © 2008 Unisonic Technologies Co., Ltd
1 of 7
QW-R204-004,H
MJE13003
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Collector-Emitter Voltage
Collector-Base Voltage
Emitter Base Voltage
SYMBOL
V
CEO(SUS)
V
CBO
V
EBO
I
C
I
CM
I
B
I
BM
I
E
I
EM
NPN SILICON TRANSISTOR
RATINGS
UNIT
400
V
700
V
9
V
Continuous
1.5
Collector Current
A
Peak (1)
3
Continuous
0.75
Base Current
A
Peak (1)
1.5
Continuous
2.25
Emitter Current
A
Peak (1)
4.5
TO-126
1.4
W
Total Power Dissipation (Ta=25°C)
TO-92
1.1
W
P
D
TO-220
40
W
Total Power Dissipation (T
C
=25°C)
TO-252
25
W
20
W
TO-251
Junction Temperature
T
J
+150
°C
Storage Temperature
T
STG
-55 ~ +150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS
(T
C
=25°C, unless otherwise specified.)
PARAMETER
OFF CHARACTERISTICS (Note)
Collector-Emitter Sustaining Voltage
Collector Cutoff Current
Emitter Cutoff Current
SECOND BREAKDOWN
Second Breakdown Collector Current
with bass forward biased
Clamped Inductive SOA with base
reverse biased
ON CHARACTERISTICS (Note)
DC Current Gain
SYMBOL
TEST CONDITIONS
MIN
400
T
C
=25°C
T
C
=100°C
1
5
1
See Figure 5
See Figure 6
I
C
=0.5A, V
CE
=2V
I
C
=1A, V
CE
=2V
I
C
=0.5A, I
B
=0.1A
I
C
=1A, I
B
=0.25A
I
C
=1.5A, I
B
=0.5A
I
C
=1A, I
B
=0.25A, T
C
=100°C
I
C
=0.5A, I
B
=0.1A
I
C
=1A, I
B
=0.25A
I
C
=1A, I
B
=0.25A, T
C
=100°C
I
C
=100mA, V
CE
=10V, f=1MHz
V
CB
=10V, I
E
=0, f=0.1MHz
8
5
40
25
0.5
1
3
1
1
1.2
1.1
10
21
TYP
MAX
UNIT
V
mA
mA
V
CEO(SUS)
I
C
=10 mA , I
B
=0
V
CEO
=Rated Value,
I
CEO
V
BE(OFF)
=1.5 V
I
EBO
V
EB
=9 V, I
C
=0
Is/b
RBSOA
h
FE1
h
FE2
V
CE(SAT
)
Collector-Emitter Saturation Voltage
V
Base-Emitter Saturation Voltage
DYNAMIC CHARACTERISTICS
Current-Gain-Bandwidth Product
Output Capacitance
SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time
Rise Time
Storage Time
Fall Time
V
BE(SAT)
V
f
T
Cob
4
MHz
pF
t
D
t
R
t
S
t
F
V
CC
=125V, I
C
=1A, I
B1
=I
B2
=0.2A,
t
P
=25μs, Duty Cycle≤1%
0.05
0.5
2
0.4
0.1
1
4
0.7
μs
μs
μs
μs
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QW-R204-004,H
MJE13003
ELECTRICAL CHARACTERISTICS(Cont.)
Inductive Load, Clamped (Table 1)
Storage Time
t
STG
Crossover Time
t
C
Fall Time
t
F
Note: Pulse Test : PW=300μs, Duty Cycle≤2%
NPN SILICON TRANSISTOR
I
C
=1A, Vclamp=300V, I
B1
=0.2A,
V
BE(OFF)
=5Vdc, T
C
=100°C
1.7
0.29
0.15
4
0.75
μs
μs
μs
CLASSIFICATION OF h
FE1
RANK
RANGE
A
8 ~ 16
B
15 ~ 21
C
20 ~ 26
D
25 ~ 31
E
30 ~ 36
F
35 ~ 40
Table 1.Test Conditions for Dynamic Performance
Reverse Bias Safe Operating Area and Inductive Switching
+5V
1N4933
0.001μF
33
MJE210
L
MR826*
Vcc
Resistive
Switching
Test Circuits
5V
P
w
DUTY CYCLE≦10%
t
R
, t
F
≦10ns
68
1k
33 1N4933
2N2222
1k
+5V
1N4933
0.02μF
270
1k
2N2905
47
1/2W
MJE200
100
-V
BE
(
OFF
)
R
B
I
B
T.U.T.
Ic
5.1k
51
V
clamp
*SELECTED FOR≣1kV
V
CE
+125V
Rc
TUT
R
B
D1
-4.0V
SCOPE
NOTE
P
W
and Vcc Adjusted for Desired Ic
R
B
Adjusted for Desired I
B1
Circuit Values
Coil Data :
V
CC
=20V
Ferroxcube core #6656
Vclamp=300V
Full Bobbin ( ~ 200 Turns) #20
GAP for 30 mH/2 A
Lcoil=50mH
V
CC
=125V
R
C
=125Ω
D1=1N5820 or
Equiv.
R
C
=47Ω
Output Waveforms
Test Waveforms
Ic
Ic(pk)
t1
tf
tf CLAMPED
t
t1 Adjusted to
Obtain Ic
t1≒
V
CE
or
Vclamp
Lcoil(Icpk)
Vcc
Test Equipment
Scope-Tektronics
475 or Equivalent
+10.3 V
25μS
0
-8.5V
tr, tf<10ns
Duty Cycly=1.0%
R
B
and Rc adjusted
for desired I
B
and Ic
V
CE
TIME
t2
t
Lcoil(Icpk)
t2≒ Vclamp
Figure 1. Inductive Switching Measurements
I
CPK
90% V
clamp
I
C
t
sv
t
RV
t
c
V
CE
I
B
90% I
B1
10% V
clamp
10%
Icpk 2% Ic
V
clamp
90% Ic
t
FI
t
TI
Table 2. Typical Inductive Switching Performance
Ic
AMP
Tc
°C
25
100
25
100
25
100
t
sv
µs
1.3
1.6
1.5
1.7
1.8
3
t
RV
µs
0.23
0.26
0.10
0.13
0.07
0.08
t
FI
µs
0.30
0.30
0.14
0.26
0.10
0.22
t
TI
µs
0.35
0.40
0.05
0.06
0.05
0.08
t
c
µs
0.30
0.36
0.16
0.29
0.16
0.28
0.5
1
1.5
Time
NOTE: All Data Recorded in the Inductive Switching
Circuit in Table 1
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QW-R204-004,H
MJE13003
SWITCHING TIMES NOTE
NPN SILICON TRANSISTOR
In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage
waveforms since they are in phase. However, for inductive loads, which are common to SWITCHMODE power
supplies and hammer drivers, current and voltage waveforms are not in phase. Therefore, separate measurements
must be made on each waveform to determine the total switching time. For this reason, the following new terms
have been defined.
t
SV
= Voltage Storage Time, 90% I
B1
to 10% Vclamp
t
RV
= Voltage Rise Time, 10 ~ 90% Vclamp
t
FI
= Current Fall Time, 90 ~ 10% I
C
t
TI
= Current Tail, 10 ~ 2% I
C
t
C
= Crossover Time, 10% Vclamp to 10% I
C
For the designer, there is minimal switching loss during storage time and the predominant switching power losses
occur during the crossover interval and can be obtained using the standard equation from AN–222:
PSWT = 1/2 V
CC
I
C
(t
C
) f
In general, t
RV
+ t
FI
≈
t
C
. However, at lower test currents this relationship may not be valid.
As is common with most switching transistors, resistive switching is specified at 25°C and has become a
benchmark for designers. However, for designers of high frequency converter circuits, the user oriented
specifications which make this a “SWITCHMODE” transistor are the inductive switching speeds (t
C
and t
SV
) which
are guaranteed at 100°C.
RESISTIVE SWITCHING PERFORMANCE
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MJE13003
SAFE OPERATING AREA INFORMATION
FORWARD BIAS
NPN SILICON TRANSISTOR
There are two limitations on the power handling ability of a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I
C
-V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Figure 5 is based on T
C
= 25°C; T
J(PK)
is variable depending on power level. Second breakdown pulse
limits are valid for duty cycles to 10% but must be derated when T
C
≥25°C.
Second breakdown limitations do not
derate the same as thermal limitations. Allowable current at the voltages shown on Figure 5.
T
J(PK)
may be calculated from the data in Figure 4. At high case temperatures, thermal limitations will reduce the
power that can be handled to values less than the limitations imposed by second breakdown.
REVERSE BIAS
For inductive loads, high voltage and high current must be sustained simultaneously during turn-off, in most cases,
with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to a safe
level at or below a specific value of collector current. This can be accomplished by several means such as active
clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as Reverse Bias Safe
Operating Area and represents the voltage-current conditions during reverse biased turn-off. This rating is verified
under clamped conditions so that the device is never subjected to an avalanche mode. Figure 6 gives PBSOA
characteristics.
The Safe Operating Area of Figures 5 and 6 are specified ratings (for these devices under the test conditions
shown.)
Figure 5. Active Region Safe Operating Area
10
5
2
1
0.5
Tc=25℃
0.2
0.1
0.05
0.02
0.01
0
0
100
200
300
dc
5.0 ms
10 ms
Figure 6. Reverse Bias Safe Operating Area
1.6
Collector Current, I
C
(A)
100μs
Collector Current, I
C
(A)
1.2
V
BE(OFF)
=9V
0.8
1.0 ms
T
J
≦100℃
I
B1
=1A
Thermal Limit(Single Pule)
Bonding Wire Limit
Second Breakdown Limit
Curves Apply Below Rated
V
CEO
0.4
5V
3V
1.5V
5
10
20
50
100
200 300
500
400
500
600
700
800
Collector-Emitter Voltage, V
CE
(V)
Collector-Emitter Clamp Voltage,V
CE
(V)
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