M58BF008
8 Mbit (256Kb x32, Burst) Flash Memory
TARGET SPECIFICATION
FEATURES SUMMARY
s
SUPPLY VOLTAGE
– V
DD
= 5V for Program, Erase and Read
– V
DDQ
= 3.3V for I/O Buffers
– V
PP
= 12V for fast Program (optional)
s
Figure 1. Packages
CONFIGURABLE OPTIONS
– Synchronous or Asynchronous write mode
– Burst Wrap
– Critical Word X (3 or 4) and Burst Word
Y (1 or 2) latency times
LBGA80 (ZA)
10 x 8 solder balls
PQFP80 (T)
BGA
s
ACCESS TIME
– Synchronous X-Y-Y-Y Burst Read
up to 40MHz
– Asynchronous Read: 90ns
s
s
PROGRAMMING TIME: 10µs typical
MEMORY BLOCKS
– 32 equal Main blocks of 256 Kbit
– One Overlay block of 256 Kbit
Figure 2. Logic Diagram
VDD VDDQ VPP
18
A17-A0
CLK
RP
E
G
GD
W
LBA
WR
BAA
M58BF008
32
DQ31-DQ0
s
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: F0h
– Version Code: 0-7h
VSS
VSSQ
AI02656B
January 2001
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.
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M58BF008
DESCRIPTION
The M58BF008 is a family of 8 Mbit non-volatile
Flash memories that can be erased electrically at
the block level and programmed in-system. Family
members are configured during product testing for
a specific Synchronous or Asynchronous Write
mode, a Burst Wrap and for Critical Word X = 3 or
4 and Burst Word Y = 1 or 2 latency times. The
Main memory array matrix allows each of the 32
equal blocks of 256 Kbit to be erased separately
and re-programmed without affecting other blocks.
The memory features a 256 Kbit Overlay block
having the same address space as the Main block
0. The Overlay block provides a secure storage
area that is controlled by special Instructions and
an external input. A separate supply V
DDQ
allows
the Input/Output signals to be at 3.3V levels, while
the main supply V
DD
is 5V.
When the V
PP
supply is at V
SS
this prevents pro-
gramming and erasure of the memory blocks and,
in addition, it prevents reading of the Overlay
block. When the V
PP
supply is at 5V it enables
both in-system program/erase and read access to
the Overlay block. For a limited time and number
of program/erase cycles the V
PP
supply may be
raised to 12V to provide fast program and erase
times.
A Command Interface decodes the Instructions
written to the memory to access or modify the
memory content, to toggle the enable/disable of
read access to the Overlay block, to toggle the
Synchronous or Asynchronous Read mode. A
Program/Erase Controller (P/E.C.) executes the
algorithms taking care of the timings necessary for
program and erase operations. The P/E.C. also
takes care of verification to unburden the system
microprocessor, while a Status Register tracks the
status of each operation.
The following Instructions are executed by the
memory in either Asynchronous or Synchronous
mode.
Access or modify memory content:
- Read Array
- Read or Clear Status Register
- Read Electronic Signature
- Erase Main memory block or Overlay block
- Program Main memory or Overlay memory
- Program Erase Suspend or Resume
Toggle:
– Asynchronous/Synchronous Read
– Overlay Block Read Enable/Disable
The M58BF008 devices are offered in PQFP80
and LBGA80 1.0mm ball pitch packages.
Table 1. Signal Names
A0-A17
DQ0-DQ31
CLK
RP
E
G
GD
W
LBA
WR
BAA
V
DD
V
DDQ
V
PP
V
SS
V
SSQ
DU
NC
Address Inputs
Data Input/Output
System Clock
Reset/Power-down
Chip Enable
Output Enable
Output Disable
Write Enable
Load Burst Address
Write/Read
Burst Address Advance
Supply Voltage
Supply Voltage for Input/Output
Buffers
Optional Supply Voltage for Fast
Program and fast Erase Operations
Ground
Input/Output Ground
Don’t Use as Internally Connected
Not Connected Internally
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M58BF008
ORGANIZATION
The M58BF008 has a data path width of 32 bit
(Double-Word) and is organised as a Main memo-
ry array of 32 blocks of 256 Kbit plus an Overlay
block of 256 Kbit having the same address space
as the Main block 0. The memory map is shown in
Table 3.
The memory is addressed by A0-A17 which are
static for Asynchronous or latched for Synchro-
nous operation. Data Input/Output is static or
latched on DQ0-DQ31, these signals output data,
status or signatures read from the memory, or they
input data to be programmed or Instruction com-
mands to the Command Interface.
Asynchronous mode
Memory control is provided by Chip Enable E, Out-
put Enable G, Output Disable GD and Write En-
able W for read and write operations.
Synchronous mode
Memory control is provided by Load Burst Address
LBA which loads a read or write address. A Syn-
chronous Single Read or a Synchronous Burst
Read is performed under control of Output Enable
G and Output Disable GD. Synchronous Write is
controlled by Write/Read Enable WR, Load Burst
Address LBA and Write Enable W. Internal ad-
vance of the burst address is controlled by Burst
Address Advance BAA.
Table 3. Block Addresses
#
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Overlay Block
Size
(Kbit)
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
256
Address Range
3E000-3FFFF
3C000-3DFFF
3A000-3BFFF
38000-39FFF
36000-37FFF
34000-35FFF
32000-33FFF
30000-31FFF
2E000-2FFFF
2C000-2DFFF
2A000-2BFFF
28000-29FFF
26000-27FFF
24000-25FFF
22000-23FFF
20000-21FFF
1E000-1FFFF
1C000-1DFFF
1A000-1BFFF
18000-19FFF
16000-17FFF
14000-15FFF
12000-13FFF
10000-11FFF
0E000-0FFFF
0C000-0DFFF
0A000-0BFFF
08000-09FFF
06000-07FFF
04000-05FFF
02000-03FFF
00000-01FFF
00000-01FFF
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