Data Sheet
PT7A6527
HDLC controller
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Features
Serial Interface Feature
•
Four independent full-duplex HDLC channels
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-
-
-
•
•
•
•
•
•
Flag generation and detection
Zero insertion and deletion
CRC generation and detection
Check for abort
Description
The ISDN Digital Exchange Controller PT7A6527 is a
serial HDLC data communication circuit with four
independent channels. Its telecommunication specific
features make it especially suited for use in variable data
rate PCM systems. In addition, the device contains
sophisticated switching functions and it implements
automatic contention resolution between packet data
from different sources. It can
-
-
-
-
-
-
Receive and transmit the HDLC data packets in a
time division multiplex bit stream.
Implement the basic HDLC functions of the layer-2
protocol, including address recognition.
Interface the data packets to the microprocessor bus.
Internal FIFO is employed to store the data packets.
Switch data between serial interfaces.
Implement different types of collision resolution.
Perform test function.
Independent time-slot assignment for each channel
ISDN Oriented Mode (IOM)
Provides FIFO up to 64 bytes each for Transmit and
Receive
Supports bus configurations by collision resolution
Address recognition
Data rate up to 4Mb/s
Microprocessor Interface Feature
•
•
•
8-bit demultiplexed and multiplexed bus interface
Suitable for Intel and Motorola microprocessor
Available package: 44-pin-PLCC
Application
•
•
•
•
Communication multiplexers
Peripheral ISDN line cards
Packet handlers
X.25 packet switching devices
Two basic configuration and four operation modes:
•
Quad connection configuration: the four HDLC
channels (A-D) are connected to individual time
multiplexed communication lines respectively.
Two Quad Connection operation modes:
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Time slot mode: time slotted highway with
programmable time slots
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Common control mode: communication line marked
by an external strobe signal
•
Single connection configuration: the four HDLC
channels are all connected to one time multiplexed
communication line. Two operation modes
-
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IOM mode: standard IOM interface with predefined
channel positions
Time slot mode: time slotted highway with
programmable time slots
Ordering Information
Part No.
PT7A6527JE
Package
Lead free 44-pin PLCC
PT0080(11/06)
1
Ver:3
Data Sheet
PT7A6527
HDLC controller
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Block Diagram
Pin Assignment
Group
Chip Timing
Power & Ground
Microprocessor Interface
I/O Interface
Symbol
DCL, FSC, TSC
GND, VCC
AD0~AD7, A0~A6, RD/DS, WR/R/W,
CS, ALE, INT, RES
CDR, RxD0, TxD0, TxD1, RxD1, RxD2,
TxD2, TxD3, RxD3
Function
Clock
Power
Data or Control
Serial Data
PT0080(11/06)
2
Ver:3
Data Sheet
PT7A6527
HDLC controller
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Pin Description
Pin No.
4
3
1
44
42
41
39
38
13
12
9
5
2
43
35
7
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A0
A1
A2
A3
A4
A5
A6
RD / DS
Type
Description
8-bit Address Data Bus.:
If the multiplexed address/data µP interface bus
mode, transfer address from µP to 6527 and data between the µP and the
PT7A6527.
In de-multiplexed mode, they interface with the system data bus.
I/O
I
Address Bus:
Interface to the system’s bus to select an internal register
for a read or write access. Only active if a demultipl-exed µP interface.
I
Read:
Intel bus mode.
Indicates
a read operation, active low.
Data Strobe:
Motorola bus mode. The rising edge marks the end of a
valid read or write operation.
Write:
Intel bus mode.
Indicates
a write operation, active low.
Read/Write:
Motorola bus mode. To distinguish between read or write
operations.
Ground.
Data Clock:
Supplies a clock signal either equal to or twice the data rate.
Frame synchronization or data strobe signal
Reset:
A high signal on this input forces the device into the reset state.
Address Latch Enable:
Intel multiplexed bus mode.
A high on this line indicates an address of the device’s internal registers
on the external address/data bus. The address is latched by the device with
the falling edge of ALE. This allows the device to be directly connected to
a microprocessor with multiplexed address/data bus.
This pin should be connected to GND, for Intel de-multiplexed bus mode,
and connected to Vcc for Motorola bus mode.
Chip Select:
A low on this line selects the device for a read/write
operation.
Interrupt Request (Open Drain):
The signal is activated when the
device requests an interrupt.
Collision data receive.
Time-Slot Control:
Supplies a control signal for an external driver.
Transmit data:
Transmit data is shifted out via these pins at standard
TTL or CMOS levels.
8
10
11
14
15
WR/R/W
GND
DCL
FSC
RES
I
Ground
I
I
I
16
ALE
I
17
19
21
22
26
24
30
32
29
25
31
34
36
6, 18, 20, 23,
27, 28, 33,
37, 40
CS
INT
CDR
TSC
TXD0
TXD1
TXD2
TXD3
RXD0
RXD1
RXD2
RXD3
Vcc
NC
I
Open Drain
I
O
O
I
Power
-
Receive data:
Serial data is received on these pins at standard TTL or
CMOS levels.
3.3V or 5V power supply.
No connection.
PT0080(11/06)
3
Ver:3
Data Sheet
PT7A6527
HDLC controller
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Typical Applications
Communication Multiplexers
The four independent serial HDLC communication channels
implemented in the PT7A6527 make the circuit suitable for
use in communication multiplexers.
The collision detection/resolution capability of the circuit
allows statistical multiplexing of packets in one or several
physical data communication channels, for example in DMI
(mode 3) applications.
Centralized Signaling / Data Packet Handlers
The PT7A6527 can be used in central packet handlers of
ISDN networks to process signaling or packet data of four
ISDN subscribers. In this application, it may be used with or
without PCM Interface Controller (PCM Controller).
The PT7A6527 can be connected to the IOM interface of the
PCM CONTROLLER, which is itself connected to the PCM
system highway. The PCM CONTROLLER implements
concentration and time slot assignment functions. As an
alternative, the PT7A6527 may be directly connected to PCM
highways (figure
1).
The size (from 1 to 8 bits) and the position of the time slot
associated with each HDLC controller is software
programmable. In addition to the receiver and transmit data
highways, the PT7A6527 accepts a third input connection for
collision detection purposes. The mode of collision detection
is programmable. A collision highway (or time slot) can be
used for remote collision control, as a clear to send lead, or for
local contention resolution among several devices.
Figure
1
Use of PT7A6527 in Central Signaling / Data Packet Handlers
PT0080(11/06)
4
Ver:3
Data Sheet
PT7A6527
HDLC controller
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Line Cards in De-Centralized or Mixed Signaling / Data
Packet Handling Architectures
The PT7A6527 can be used on peripheral line cards to process
D-channel packets for ISDN subscribers. The PCM Controller
has the layer-1 controlling capacity and a B-channel switching
capacity for a total of 32 subscribers. The B and D channels
and the control information for eight subscribers are carried by
one IOM interface. Thus a line card dimensioned for 32-ISDN
subscribers may employ up to eight devices, two for each
IOM connection (figure
2).
A High Level Serial
Communication Controller (6525) with two HDLC channels,
or another PT7A6527 may be used to transmit and receive
signaling via the system highway in a common channel. Again,
such a common channel may be shared among several line
cards, due to the statistical multiplexing capability of these
controllers.
In completely de-centralized D-channel processing
architectures, the processing capacity of a line card is usually
dimensioned so as to avoid blocking situations even under
maximum conceivable D-channel traffic conditions. It may
sometimes be more advantageous to perform p-packet
handling in a centralized manner while keeping s-packet
handling on the line cards. A statistical increase in p-packet
traffic has then no effect on the line card, and can be easily
dealt with by one of the modular architectures for a central
packet handler shown in the previous section. A more
effective sharing of the total p-packet handling capacity is the
result, especially in a situation where p-packet traffic patterns
vary widely from one subscriber group to another.
The use of a PT7A6527 in the mixed D-channel processing
architecture is illustrated in
figure 3.
The additional transparent data connections supported by the
PT7A6527 enable a merging of p and s packets into one D
channel. Possible collision situations are dealt with by the
PT7A6527 which uses either the additional collision detect
line (figure
3)
or a time slot on the system highway (figure
3)
from the line card to the central packet handler.
Figure 2 Line Card in a De-Centralized D-channel Handing Architecture
Line Transceivers
S/U
B
X8
D
S/U
D
C/I, MONITOR
PT7A6555
System
Highways
c.c.s + c.c.p
PT7A6527
PT7A6527
s, p
D
s, p
µP
D
PT7A6527/
PT7A652
Note:
c.c.s/p=Common channel for signaling and for packed data, respectively
C/I,MON=Command/Indication and MONITOR channels forthe interface
PT0080(11/06)
5
Ver:3
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