any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein.
Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for
products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
RLDRAM
is a registered trademark of Micron Technology, Inc.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 00A, 9/10/2014
1
IS49NLS96400A, IS49NLS18320A
1 Package Ballout and Description
1.1 576Mb (64Mx9) Separate I/O BGA Ball-out (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
A22
A5
A8
BA2
NF
2
1
2
V
SS
DNU
DNU
DNU
DNU
A6
A9
NF
2
3
3
3
3
3
V
EXT
DNU
DNU
DNU
DNU
A7
V
SS
V
DD
V
DD
V
SS
A17
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
V
EXT
3
3
3
3
4
V
SS
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
SS
5
6
7
8
9
V
SS
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
SS
10
V
EXT
Q0
Q1
QK0#
Q2
Q3
A2
V
SS
V
DD
V
DD
V
SS
A12
Q4
Q5
Q6
Q7
Q8
V
EXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D4
D5
D6
D7
D8
TD0
12
TCK
V
DD
V
TT
V
SS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
A21
DNU
3
DNU
3
DK
REF#
WE#
A18
A15
V
SS
V
TT
V
DD
V
REF
DK#
CS#
A16
DNU
3
DNU
3
DNU
3
DNU
3
DNU
3
ZQ
Notes:
1. Reserved for future use. This may optionally be connected to GND.
2. No Function. This signal is internally connected and has parasitic characteristics of a
clock input signal. This may optionally be connected to GND.
3. Do not use. This signal is internally connected and has parasitic characteristics of a
I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins are High-Z.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 00A, 9/10/2014
2
IS49NLS96400A, IS49NLS18320A
1.2 576Mb (32Mx18) Separate I/O BGA Ball-out (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
REF
V
DD
V
TT
A22
A21
A5
A8
BA2
NF
3
1
2
2
V
SS
D4
D5
D6
D7
D8
A6
A9
NF
3
3
V
EXT
Q4
Q5
Q6
Q7
Q8
A7
V
SS
V
DD
V
DD
V
SS
A17
Q14
Q15
QK1#
Q16
Q17
V
EXT
4
V
SS
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
SS
5
6
7
8
9
V
SS
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DD
V
SS
V
DD
V
DD
V
SS
V
DD
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
SS
10
V
EXT
Q0
Q1
QK0#
Q2
Q3
A2
V
SS
V
DD
V
DD
V
SS
A12
Q9
Q10
Q11
Q12
Q13
V
EXT
11
TMS
D0
D1
QK0
D2
D3
A1
A4
BA0
BA1
A14
A11
D9
D10
D11
D12
D13
TD0
12
TCK
V
DD
V
TT
V
SS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
V
SS
V
TT
V
DD
TDI
DK
REF#
WE#
A18
A15
V
SS
V
TT
V
DD
V
REF
DK#
CS#
A16
D14
D15
QK1
D16
D17
ZQ
Notes: 1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an
address input signal. This may optionally be connected to GND.
3. No Function. This signal is internally connected and has parasitic characteristics of a
clock input signal. This may optionally be connected to GND.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 00A, 9/10/2014
3
IS49NLS96400A, IS49NLS18320A
1.3 Ball Descriptions
Symbol
A0-A21
BA0-BA2
CK, CK#
Type
Input
Input
Input
Description
Address inputs:
Defines the row and column addresses for READ and WRITE operations. During a
MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising
edge of CK.
Bank address inputs:
Selects to which internal bank a command is being applied to.
Input clock:
CK and CK# are differential input clocks. Addresses and commands are latched on the
rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Chip select:
CS# enables the command decoder when LOW and disables it when HIGH. When the
command decoder is disabled, new commands are ignored, but internal operations continue.
Data input:
The D signals form THE 18-bit input data bus. During WRITE commands, the data is
sampled at both edges of DK.
Input data clock:
DK* and DK*# are the differential input data clocks. All input data is referenced to both
edges of DK*. DK*# is ideally 180 degrees out of phase with DK*. For the x36 device, DQ0–DQ17 are
referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the x9 and x18
devices, all DQ* are referenced to DK and DK#. All DK* and DK*# pins must always be supplied to the
device.
Input data mask:
The DM signal is the input mask signal for WRITE data. Input data is masked when DM
is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to
ground if not used.
IEEE 1149.1 clock input:
This ball must be tied to V
SS
if the JTAG function is not used.
IEEE 1149.1 test inputs:
These balls may be left as no connects if the JTAG function is not used.
Command inputs:
Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the
command to be executed.
Data output:
The Q signals form THE 18-bit output data bus. During READ commands, the data is
referenced to both edges of QK.
Input reference voltage:
Nominally V
DDQ
/2. Provides a reference voltage for the input buffers.
External impedance (25–60Ω):
This signal is used to tune the device outputs to the system data bus
impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the minimum impedance mode.
Output data clocks:
QK* and QK*# are opposite polarity, output data clocks. They are free running, and
during READs, are edge-aligned with data output from the memory. QK*# is ideally 180 degrees out of
phase with QK*. For the x36 device, QK0 and QK0# are aligned with DQ0-DQ17, and QK1 and QK1# are
aligned with DQ18-DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0-DQ8, while QK1 and
QK1# are aligned with Q9-Q17. For the x9 device, all DQs are aligned with QK0 and QK0#.
Data valid:
The QVLD pin indicates valid output data. QVLD is edge-aligned with QK* and QK*#.
IEEE 1149.1 test output:
JTAG output. This ball may be left as no connect if the JTAG function is not
used.
CS#
Input
D0-D17
Input
DK, DK#
Input
DM
Input
TCK
TMS,TDI
WE#,
REF#
Q0-Q17
V
REF
Input
Input
Input
Input
Input
ZQ
I/O
QK
X
, QK
X
#
Output
QVLD
TDO
Output
Output
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 00A, 9/10/2014
4
IS49NLS96400A, IS49NLS18320A
V
DD
V
DDQ
V
EXT
V
SS
V
SSQ
V
TT
A22
DNU
NF
Supply
Supply
Supply
Supply
Supply
Supply
-
-
-
Power supply:
Nominally, 1.8V.
DQ power supply:
Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
Power supply:
Nominally, 2.5V.
Ground.
DQ ground:
Isolated on the device for improved noise immunity.
Power supply:
Isolated termination supply. Nominally, V
DDQ
/2.
Reserved for future use:
This signal is not connected and can be connected to ground.
Do not use:
These balls may be connected to ground. Note that if ODT is enabled, these pins are High-Z.
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