Serial EEPROM Series
High Reliability Series
EEPROMs I2C BUS
BR24A□□-WM series
●Description
BR24A□□-WM series is a serial EEPROM of I
2
C BUS interface method.
●Features
2
1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock(SCL) and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port
3) 2.5V~5.5V single power source action most suitable for battery use
4) Page write mode useful for initial value write at factory shipment
5) Highly reliable connection by Au pad and Au wire
6) Auto erase and auto end function at data rewrite
7) Low current consumption
*1
At write operation (5V)
: 1.2mA (Typ.)
At read operation (5V)
: 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) SOP8/SOP-J8/MSOP8 compact package
*2
10) Data rewrite up to 100,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
*1 BR24A32-WM,BR24A64-WM : 1.5mA
*2 Refer to following list
No.09001ECT02
●Page
write
Number of Pages
Product
number
8Byte
BR24A01A-WM
BR24A02-WM
16Byte
BR24A04-WM
BR24A08-WM
BR24A16-WM
32Byte
BR24A32-WM
BR24A64-WM
●BR24A
series
Capacity
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
32Kbit
64Kbit
Bit format
128×8
256×8
512×8
1K×8
2K×8
4K×8
8K×8
Type
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
Power source Voltage
2.5½5.5V
2.5½5.5V
2.5½5.5V
2.5½5.5V
2.5½5.5V
2.5½5.5V
2.5½5.5V
SOP8
●
●
●
●
●
●
●
SOP-J8
●
●
●
●
●
MSOP8
●
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
1/17
2009.08 - Rev.C
BR24A□□-WM series
●Absolute
maximum ratings (Ta=25℃)
Parameter
Impressed voltage
Permissible dissipation
Storage temperature range
Action temperature range
Terminal voltage
●Memory
cell characteristics (VCC=2.5½5.5V)
Parameter
Number of data rewrite times
*1
Data hold years
*1
○Shipment
data all address FFh
*1 Not 100% TESTED
Technical Note
symbol
VCC
Pd
Tstg
Topr
-
Limits
-0.3½+6.5
450 (SOP8)
*1
450 (SOP-J8)
*2
310 (MSOP8)
*3
-65½+125
-40½+105
-0.3½VCC+1.0
Unit
V
mW
℃
℃
V
When using at Ta=25℃ or higher, 4.5mW(*1,*2) , 3.1mW(*3) to be reduced per 1℃
Min.
100,000
40
Limits
Typ.
-
-
Max.
-
-
Unit
Times
Years
Test Condition
Ta=-40½105℃
Ta=25℃
●Recommended
operating conditions
Parameter
Power source voltage
Input voltage
Symbol
VCC
V
IN
Limits
2.5½5.5
0½VCC
Unit
V
●Electrical
characteristics (Unless otherwise specified, Ta=-40½+105℃, VCC=2.5½5.5V)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
“HIGH” input voltage
V
IH
0.7VCC
-
-
V
“LOW” input voltage
V
IL
-
-
0.3 VCC
V
“LOW” output voltage 1
V
OL
-
-
0.4
V
I
OL
=3.0mA (SDA)
Input leak current
I
LI
-1
-
1
μA
V
IN
=0V½VCC
Output leak current
I
LO
-1
-
1
μA
V
OUT
=0V½VCC, (SDA)
*1
2.0
VCC=5.5V,f
SCL
=400kHz, t
WR
=5ms,
I
CC1
-
-
mA
*2
Byte write, Page write
Current consumption
3.0
at action
VCC=5.5V,f
SCL
=400kHz
I
CC2
-
-
0.5
mA
Random read, current read, sequential read
VCC=5.5V, SDA・SCL=VCC
Standby current
I
SB
-
-
2.0
μA
A0, A1, A2=GND, WP=GND
◎Radiation
resistance design is not made.
*1 BR24A01A/02/04/08/16-WM, *2 BR24A32/64-WM
●Action
timing characteristics
(Unless otherwise specified, Ta=
-
40½+105℃, VCC=2.5½5.5V)
FAST-MODE
STANDARD-MODE
2.5V≦VCC≦5.5V
2.5V≦VCC≦5.5V
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
SCL frequency
f
SCL
-
-
400
-
-
100
Data clock “HIGH“ time
t
HIGH
0.6
-
-
4.0
-
-
Data clock “LOW“ time
t
LOW
1.2
-
-
4.7
-
-
*1
SDA, SCL rise time
t
R
-
-
0.3
-
-
1.0
*1
SDA, SCL fall time
tF
-
-
0.3
-
-
0.3
Start condition hold time
t
HD:STA
0.6
-
-
4.0
-
-
Start condition setup time
t
SU:STA
0.6
-
-
4.7
-
-
Input data hold time
t
HD:DAT
0
-
-
0
-
-
Input data setup time
t
SU:DAT
100
-
-
250
-
-
Output data delay time
t
PD
0.1
-
0.9
0.2
-
3.5
Output data hold time
t
DH
0.1
-
-
0.2
-
-
Stop condition setup time
t
SU:STO
0.6
-
-
4.7
-
-
Bus release time before transfer start
tB
UF
1.2
-
-
4.7
-
-
Internal write cycle time
t
WR
-
-
5
-
-
5
Noise removal valid period (SDA, SCL terminal)
tI
-
-
0.1
-
-
0.1
WP hold time
t
HD:WP
0
-
-
0
-
-
WP setup time
t
SU:WP
0.1
-
-
0.1
-
-
WP valid time
t
HIGH:WP
1.0
-
-
1.0
-
-
*1 Not 100% tested
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
ns
μs
μs
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
2/17
2009.08 - Rev.C
BR24A□□-WM series
Technical Note
●FAST-MODE
and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds.
100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the
maximum action frequency, so 100kHz clock may be used in FAST-MODE. At VCC=2.5V½5.5V , 400kHz, namely, action is
made in FASTMODE. (Action is made also in STANDARD-MODE.)
●Sync
data input / output timing
tR
SCL
tHD:STA
SDA
(入力)
(input)
tBUF
(output)
(出力)
tF
tHIGH
SCL
tSU:DAT
tLOW
tHD:DAT
tSU:STA
SDA
tHD:STA
tSU:STO
tPD
tDH
SDA
START BIT
STOP BIT
○Input
read at the rise edge of SCL
○Data
output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
Fig.1-(b) Start-stop bit timing
SCL
SCL
SDA
D0
Write data
DATA(1)
D1
D0
ACK
ACK
½WR
Stop condition
Start condition
DATA(n)
ACK
½WR
SDA
(n-th
address)
WP
Stop condition
ストップコンディション
tSU：WP
½HD：WP
Fig.1-(c) Write cycle timing
Fig.1-(d) WP timing at write execution
SCL
DATA(1)
SDA
D1
D0
ACK
tHIGH:WP
WP
DATA(n)
ACK
tWR
○At
write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By
setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
Fig.1-(e) WP timing at write cancel
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
3/17
2009.08 - Rev.C
BR24A□□-WM series
●Block
diagram
Technical Note
*2
A0
1
*1
1Kbit~64Kbit EEPROM array
7bit 11bit
8bit 12bit
9bit 13b
it
10bi
t
8
8bit
Vcc
*2
A1
2
Address
decoder
*1
7bit 11bit
8bit 12bit
9bit 13b
it
10bi
t
Slave - word
address register
Data
register
7
WP
*2
A2
3
START
STOP
Control circuit
ACK
6
SCL
GND
4
＊
1
High voltage
generating circuit
7bit : BR24A01A-WM
8bit : BR24A02-WM
9bit : BR24A04-WM
Power source
voltage detection
10bit : BR24A08-WM
11bit : BR24A16-WM
12bit : BR24A32-WM
13bit : BR24A64-WM
＊
5
: BR24A04-WM
: BR24A08-WM
: BR24A16-WM
SDA
2
A0=N.C.
A0, A1=N.C.
A0, A1= N.C. A2=Don’t Use
Fig.2 Block diagram
●Pin
assignment and description
A0
A1
A2
GND
1
2
3
4
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
8
7
6
5
Vcc
WP
SCL
SDA
Terminal
name
A0
A1
A2
GND
SDA
SCL
WP
Vcc
Input /
output
Input
Input
Input
-
Input /
output
Input
Input
-
Function
BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM
Slave address setting
Slave address setting
Slave address setting
Not connected
Not connected
Not used
Slave address setting
Slave address setting
Slave address setting
Reference voltage of all input / output, 0V
Slave and word address, Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
4/17
2009.08 - Rev.C
BR24A□□-WM series
●Characteristic
data (The following values are Typ. ones.)
6
5
4
VIH1,2[V]
3
2
1
0
0
3
4
5
6
Vcc[V]
Fig.3 H input voltage VIH1,2 (SCL,SDA,WP)
1.2
SPEC
SPEC
SPEC
Technical Note
6
5
4
VIL1,2[V]
3
2
1
0
1
2
0
3
4
5
6
Vcc[V]
Fig.4 L input voltageVIL1,2 (SCL,SDA,WP)
1
2
SPEC
Ta=105℃
Ta=-40℃
Ta=25℃
1
0.8
VOL1[V]
0.6
SPEC
Ta=105℃
Ta=25℃
0.4
0.2
Ta=105℃
Ta=-40℃
Ta=25℃
Ta=-40℃
0
0
3
4
5
6
IOL1[mA]
Fig.5 L output voltage VOL1-IOL1 (VCC=2.5V)
1
2
1.2
1
0.8
ILI[μA]
ILO[μA]
0.6
0.4
0.2
0
0
3
4
5
Vcc[V]
Fig.6 Input leak current ILI (SCL,WP)
1
2
6
Ta=105℃
Ta=25℃
Ta=-40℃
2.5
[BR24A01/02/04/08/16 series]
1
0.8
0.6
0.4
0.2
0
0
1
2
3
Vcc[V]
4
5
6
Ta=105℃
Ta=25℃
Ta=-40℃
2
ICC1[mA]
1.5
1
0.5
0
0
fSCL=400kHz
DATA=AAh
SPEC
Ta=25℃
Ta=105℃
Ta=-40℃
Fig.7 Output leak current ILO(SDA)
3
4
5
6
Vcc[V]
Fig.8 Current consumption at WRITE action ICC1
(fscl=400kHz)
[BR24A01/02/04/08/16 series]
1
2
3.5
[BR24A32/64 series]
0.6
SPEC
fSCL=400kHz
DATA=AAh
SPEC
2.5
fSCL=400kHz
DATA=AAh
3
2.5
ICC1[mA]
2
1.5
1
0.5
0
0
0.5
ICC2[mA]
0.4
0.3
0.2
0.1
0
2
ICC1[mA]
1.5
1
0.5
0
fSCL=100kHz
DATA=AAh
SPEC
Ta=105℃
Ta=25℃
Ta=25℃
Ta=105℃
Ta=-40℃
Ta=-40℃
Ta=25℃
Ta=105℃
Ta=-40℃
1
2
3
Vcc[V]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
Fig.9 Current consumption at WRITE action ICC1
(fSCL=400kHz)
3.5
[BR24A32/64 series]
Fig.10 Current consumption at READ action ICC2
(fSCL=400kHz)
0.6
SPEC
Fig.11 Current consumption at WRITE action ICC1
(fSCL=100kHz)
2.5
SPEC
3
2.5
ICC1[mA]
2
1.5
1
0.5
0
0
1
2
3
Vcc[V]
4
5
6
Ta=25℃
Ta=105℃
Ta=-40℃
fSCL=100kHz
DATA=AAh
SPEC
0.5
ICC2[mA]
0.4
0.3
0.2
0.1
0
0
3
4
5
6
Vcc[V]
Fig.13 Current consumption at READ action ICC2
(fSCL=100kHz)
1
2
Ta=105℃
Ta=25℃
fSCL=100kHz
DATA=AAh
2
ISB[μA]
1.5
1
0.5
Ta=-40℃
Ta=105℃
Ta=-40℃
Ta=25℃
0
0
1
2
3
Vcc[V]
4
5
6
Fig.12 Current consumption at WRITE action ICC1
(fSCL=100kHz)
10000
5
Fig.14 Standby current ISB
5
SPEC2
SPEC2
1000
fSCL[kHz]
4
tHIGH [μs]
tLOW[μs]
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC1
4
3
2
1
0
0
1
2
3
Vcc[V]
4
5
6
0
3
4
5
Vcc[V]
Fig.17 Data clock "L" time tLOW
1
2
6
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC1
3
2
1
0
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC1
100
SPEC2
10
1
0
1
2
3
Vcc[V]
4
5
6
Fig.15 SCL frequency fSCL
5
SPEC2
Fig.16 Data clock "H" time tHIGH
6
5
tSU:STA[μs]
4
3
2
1
0
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC2
50
SPEC1,2
tHD:DAT(HIGH)[ns]
4
tHD:STA[μs]
3
2
1
0
0
1
2
3
Vcc[V]
4
5
6
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC1
0
-50
Ta=-40℃
Ta=25℃
Ta=105℃
-100
-150
-200
SPEC1
0
1
2
3
Vcc[V]
4
5
6
0
1
2
3
Vcc[V]
4
5
6
Fig.18 Start condition hold time tHD:STA
Fig.19 Start condition setup time tSU:STA
Fig.20 Input data hold time tHD:DAT(HIGH)
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
5/17
2009.08 - Rev.C
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
