HM5225165B-75/A6/B6
HM5225805B-75/A6/B6
HM5225405B-75/A6/B6
256M LVTTL interface SDRAM
133 MHz/100 MHz
4-Mword
×
16-bit
×
4-bank/8-Mword
×
8-bit
×
4-bank
/16-Mword
×
4-bit
×
4-bank
PC/133, PC/100 SDRAM
ADE-203-1073A (Z)
Preliminary
Rev. 0.1
Nov. 25, 1999
Description
The Hitachi HM5225165B is a 256-Mbit SDRAM organized as 4194304-word
×
16-bit
×
4 bank. The
Hitachi HM5225805B is a 256-Mbit SDRAM organized as 8388608-word
×
8-bit
×
4 bank. The Hitachi
HM5225405B is a 256-Mbit SDRAM organized as 16777216-word
×
4-bit
×
4 bank. All inputs and outputs
are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
•
•
•
•
•
•
•
•
3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed
RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
Sequential (BL = 1/2/4/8)
Interleave (BL = 1/2/4/8)
•
Programmable
CAS
latency: 2/3
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
•
Byte control by DQM : DQM (HM5225805B/HM5225405B)
: DQMU/DQML (HM5225165B)
•
Refresh cycles: 8192 refresh cycles/64 ms
•
2 variations of refresh
Auto refresh
Self refresh
Ordering Information
Type No.
HM5225165BTT-75*
1
HM5225165BTT-A6
HM5225165BTT-B6*
2
HM5225165BLTT-75*
1
HM5225165BLTT-A6
HM5225165BLTT-B6*
2
HM5225805BTT-75*
1
HM5225805BTT-A6
HM5225805BTT-B6*
2
HM5225805BLTT-75*
1
HM5225805BLTT-A6
HM5225805BLTT-B6*
2
HM5225405BTT-75*
1
HM5225405BTT-A6
HM5225405BTT-B6*
2
HM5225405BLTT-75*
1
HM5225405BLTT-A6
HM5225405BLTT-B6*
2
Frequency
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
100 MHz
CAS
latency
3
2/3
3
3
2/3
3
3
2/3
3
3
2/3
3
3
2/3
3
3
2/3
3
Package
400-mil 54-pin plastic TSOP II (TTP-54D)
Notes: 1. 100 MHz operation at
CAS
latency = 2
2. 66 MHz operation at
CAS
latency = 2
2
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Pin Arrangement
(HM5225165B)
54-pin TSOP
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
DQML
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(Top view)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
V
SS
NC
DQMU
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
Pin Description
Pin name
A0 to A12,
BA0, BA1
Function
Address input
Row address
Column address
Bank select address
DQ0 to DQ15
CS
RAS
CAS
Data-input/output
Chip select
Row address strobe command
Column address strobe command
A0 to A12
A0 to A8
BA0/BA1 (BS)
Pin name
WE
DQMU/DQML
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Write enable
Input/output mask
Clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
3
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Pin Arrangement
(HM5225805B)
54-pin TSOP
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(Top view)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
CC
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
Pin Description
Pin name
A0 to A12,
BA0, BA1
Function
Address input
Row address
Column address
Bank select address
DQ0 to DQ7
CS
RAS
CAS
Data-input/output
Chip select
Row address strobe command
Column address strobe command
A0 to A12
A0 to A9
BA0/BA1 (BS)
Pin name
WE
DQM
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Write enable
Input/output mask
Clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
4
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Pin Arrangement
(HM5225405B)
54-pin TSOP
V
CC
NC
V
CC
Q
NC
DQ0
V
SS
Q
NC
NC
V
CC
Q
NC
DQ1
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(Top view)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SS
Q
NC
DQ3
V
CC
Q
NC
NC
V
SS
Q
NC
DQ2
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
Pin Description
Pin name
A0 to A12,
BA0, BA1
Function
Address input
Row address
Column address
Bank select address
DQ0 to DQ3
CS
RAS
CAS
Data-input/output
Chip select
Row address strobe command
Column address strobe command
A0 to A12
A0 to A9, A11
BA0/BA1 (BS)
Pin name
WE
DQM
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
Write enable
Input/output mask
Clock input
Clock enable
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
5
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
