THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
MV1443
PRELIMINARY INFORMATION
DS3107 2.2
MV1443
PCM TIMESLOT ZERO TRANSMITTER AND RECEIVER
The MV1443 combines the Timeslot Zero Transmitter and
Receiver functions required by a 2.048Mbit 30 channel PCM
transmission link operating in accordance with the appropriate
CCITT Recommendations and forms part of the GPS 2Mbit
PCM signalling series of devices. The circuit is fabricated in
CMOS and operates from a single +5V supply with all inputs
and outputs being TTL compatible.
The Timeslot Zero Transmitter half of the circuit is
responsible for generating the timeslot zero synchronising
word of a 2Mbit PCM link in accordance with CCITT
Recommendation G.704. This function is performed by
alternately generating sync frames, containing the CCITT
Frame Alignment Signal, and non-sync frames containing user
data bits.
The Timeslot Zero Receiver function searches for the
CCITT Frame Alignment signal in the incoming data stream
and when this is present the receiver synchronises itself to this
pattern in accordance with the Frame Alignment strategy
detailed in CCITT Recommendation G.732. Once frame
alignment has been achieved the Timeslot Zero Receiver
produces various timing outputs for the use of external circuitry
and extracts the user data bits of timeslot zero.
GND1
RST
D
TZS-RZ
NC
Q1N
Q1S
FRS
Q
CLK-TZ
D8N
D7N
D6N
D5N
D4N
D3N
D1N
D1S
TZS-TZ
GND2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
VDD
CLK-RZ
NC
Q8N
Q7N
Q6N
Q5N
Q4N
Q3N
CRC
SA
ER
RAI
FRS15
FRS13
NC
CK8
CCR
STM
TSZ
MV
31
1443
30
29
28
27
26
25
24
23
22
21
DG40, DP40
FEATURES
VDD
Q8N
Q7N
Q6N
Q5N
Q4N
Q3N
CRC
SA
ER
RAI
FRS15
FRS13
NC
38
37
36
35
34
33
32
31
30
NC
RST
NC
NC
s
Transmitter generates Frame Alignment Signal in
accordance with CCITT Recommendation G.704.
s
Enables access to User Data Bits of Timeslot Zero.
s
Receiver Frame Synchronisation carried out in accordance
with CCITT Recommendation G.732.
s
Provides Alarm Outputs for Reception of Corrupted
Alignment word and Loss of Frame Alignment.
s
Extracts the International Spare Bits from Alternate
Frames or from Frames 13 and 15 of the CCITT CRC
multiframe.
6
NC
Q1N
Q1S
FRS
Q
CLK-TZ
D8N
D7N
D6N
D5N
D4N
7
8
9
10
11
12
13
14
15
16
5
4
3
2
1
44 43 42 41 40
39
MV
1443
17
29
18 19 20 21 22 23 24 25 26 27 28
GND2
TSZ
STM
CCR
TZS-TZ
D3N
D1N
D1S
CK8
NC
ABSOLUTE MAXIMUM RATINGS
The absolute maximum ratings are limiting values above
which operating life may be shortened or specified parameters
may be degraded.
NC
D
s
All Inputs and Outputs TTL compatible.
CLK-RZ
TZS-RZ
s
Single +5V supply.
GND1
HG44, HP44
Fig. 1 Pin connections - top view
ELECTRICAL RATINGS
Supply Voltage
Input Voltage
Output Voltage
-0.5V to +7V
-0.5V to VDD +0.5V
-0.5V to VDD +0.5V
1
MV1443
D8N
D6N
D7N
D5N
D4N
D3N
Q
TZS-TZ
ER
SA
RAI
D1S
Timeslot Zero
Transmitter
Q8N
Q7N
Q6N
Q5N
Q4N
D1N
CLK-TZ
FRS
Timeslot
Zero
Receiver
Q3N
Q1N
Q1S
TSZ
TZS-RZ
CCR
CK8
VDD
GND1
GND2
STM
Fig. 2 Block diagram
CLK-RZ
D
RST
FRS15
FRS13
CRC
FUNCTIONAL DESCRIPTION
The MV1443 combines the Timeslot Zero Transmitter and
Receiver functions required by a 2.048Mbit 30 channel PCM
transmission link operating in accordance with the appropriate
CCITT Recommendations. The block diagram of the MV1443
is shown in Fig.2 and the function of each block is now
described separately.
Timeslot Zero Transmitter
The Timeslot Zero Transmitter circuit generates the
timeslot zero synchronising word required by a 2.048Mbit PCM
link in accordance with CCITT Recommendation G.704.
During alternate frames, denoted sync frames, the CCITT
Frame Alignment Signal (FAS - 0011011) is combined with the
International / CRC data bit input, D1S, for bit 1 and injected on
to the PCM highway via the Q output. During the other
interleaved frames, denoted non-sync frames, bit 2 of timeslot
zero is set to ‘1’ to avoid imitation of the FAS and this is
combined with the second International / CRC data bit, D1N,
for bit 1 and the user data bits, D3N-D8N, for bits 3 to 8, and
again injected on to the PCM highway.
In order to perform this function the Timeslot Zero
Transmitter requires 2 timing inputs in addition to the parallel
data bit inputs, pins CLK-TZ and FRS. The CLK-TZ input is a
2.048MHz clock input whilst FRS is a high going pulse, 8 clock
periods long, which is required to mask timeslot zero of each
frame. In addition to the PCM data stream output the Timeslot
Zero Transmitter produces a timing output, TZS-TZ, which
changes state one clock period after the end of Timeslot Zero
and is high during the transmission of timeslot zero of sync
frames.
The timing diagram of the Timeslot Zero Transmitter circuit
is shown in Fig.3.
Timeslot Zero Receiver
The Timeslot Zero Receiver circuit is responsible for
searching for and locking on to the CCITT Frame Alignment
Signal present in timeslot zero of the PCM data stream being
clocked in to its D input. This process is carried out in
accordance with the loss and recovery of frame alignment
strategy described in CCITT Recommendation G.732. Once
frame alignment has been achieved the Timeslot Zero
Receiver circuit outputs various timing reference signals for
the synchronisation of external circuitry. These timing outputs
will all free run if frame synchronisation is subsequently lost. In
addition, a control input, RST, may be used to reset this
synchronisation process, forcing the receiver out of frame
alignment.
The Timeslot Zero Receiver circuit produces 4 timing
outputs for use by external circuitry if required. The first of
these timing outputs is TSZ which is an 8 clock period long,
high going pulse masking the position of timeslot zero, similar
to the FRS input of the Timeslot Zero Transmitter, and
facilitates the frame alignment of external circuitry. The second
timing output, TZS-RZ, is a 4KHz signal which changes state
once per frame, one clock period after the end of timeslot zero,
and is high during sync frames to allow sync and non-sync
frames to be distinguished. The third timing output, CCR, is a
low going pulse, one clock period wide, occurring during 1 bit,
timeslot 1 of sync frames. The final timing output, CK8, is an
8KHz signal going low at the end of bit 7 of each timeslot zero
and high at the end of bit 7 in each timeslot 16.
2
MV1443
In addition to these timing outputs, two alarm outputs are
provided to indicate errors in the incoming data stream. The
first of these alarms, ER, goes high for one frame following a
sync frame in which a corrupted FAS was detected when the
receiver is in sync. Three consecutive alarms of this type will
put the receiver out of sync. The second alarm, SA, goes high
to indicate that the Timeslot Zero Receiver is out of frame
alignment.
In addition to the frame synchronisation process, the
Timeslot Zero Receiver is also responsible for extracting the
user data bits of non-sync words and the two International /
CRC bits of timeslot zero. The user data bits present in bits 3 to
8 of timeslot zero of non-sync frames are extracted and output
on the Q3N-Q8N parallel data outputs. The third bit of non-
sync words, Q3N, is used as the remote alarm bit in 2Mbit
PCM systems and a third alarm output, RAI, is derived from
this bit. This alarm is a persistence checked version of Q3N
which goes high when two consecutive Q3N bits have been
received high whilst the receiver is in sync. The Timeslot Zero
Receiver also extracts the data present in bit 1 of timeslot zero
under control of the CRC input. This input selects between
CCITT CRC-4 and non-CRC-4 modes of operation. In non-
CRC-4 mode, the international spare bits are extracted from bit
1 of all sync and non-sync frames and output on pins Q1S and
Q1N respectively. In CRC-4 mode, these data outputs are
extracted from bit 1 of frames 13 and 15 of the CCITT CRC-4
multiframe structure respectively. In order to accomplish this,
two timing inputs, FRS13 and FRS15, are required in CRC-4
mode. These inputs are required to be high during bit 8 of the
appropriate frame, low during bit 8 of any other non-sync frame
and any state elsewhere. The timing diagrams for the Timeslot
Zero Receiver are shown in Fig.4
CLK-TZ
FRS
TZS-TZ
D1S
Q
d1s
d1s
0
0
1
1
0
1
1
Transmitting timeslot zero-sync. word
CLK-TZ
FRS
TZS-TZ
D1N
D3N-8N
Q
d1n
d3-d8
d1n
1
d3
d4
d5
d6
d7
d8
Transmitting timeslot zero non-sync. word
Fig. 3 Timeslot zero transmitter timing
3
MV1443
125µs
125µs
CLK-RZ
D
d1s
0
0
1
1
0
1
1
d1n 1 d3n d4n d5n d6n d7n d8n
d1s
0
0
1
1
0
1
1
TSZ
TZS-RZ
CK8
CCR
Q1S
Q1N
Q3N-Q8N
d1n, d3n, - d8n
d1s
MV1443 first coming into sync., generating timing signals (non-CRC mode)
125µs
SYNC
NON-SYNC
FR13
SYNC
FR14
NON-SYNC
FR15
SYNC
FR0
TSZ
TZS-RZ
FRS13
FRS15
D
d1s
d1n
Q1S
d1s
Q1N
d1n
MV1443 extracting Signalling Data (CRC mode)
125µs
SYNC
WORD
NON
SYNC
WORD
SYNC
WORD
NON
SYNC
WORD
Bit3 = 1
BAD
SYNC
WORD
NON
SYNC
WORD
Bit3 = 1
BAD
SYNC
WORD
NON
SYNC
WORD
Bit3 = 0
BAD
SYNC
WORD
TSZ
TZS-RZ
SA
ER
RAI
MV1443 synchronisation process
Fig. 4 Timeslot zero receiver timing
4
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