®
ISO-CMOS ST-BUS™ FAMILY
MT8980D
Digital Switch
Features
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Mitel ST-BUS compatible
8-line x 32-channel inputs
8-line x 32-channel outputs
MT8980DE
MT8980DP
ISSUE8
March 1997
Ordering Information
40 Pin Plastic DIP
44 Pin PLCC
-40°C to +85°C
Description
256 ports non-blocking switch
Single power supply (+5 V)
Low power consumption: 30 mW Typ.
Microprocessor-control interface
Three-state serial outputs
This VLSI ISO-CMOS device is designed for
switching PCM-encoded voice or
data, under
microprocessor control, in a modern digital
exchange, PBX or Central Office. It provides
simultaneous connections for up to 256 64 kbit/s
channels. Each of the eight serial inputs and outputs
consist of 32 64 kbit/s channels multiplexed to form a
2048 kbit/s ST-BUS stream. In addition, the MT8980
provides microprocessor read and write access to
individual ST-BUS channels.
C4i
F0i
V
DD
V
SS
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
Serial
to
Parallel
Converter
Data
Memory
Frame
Counter
Output
MUX
Parallel
to
Serial
Converter
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
Control Register
Connection
Memory
Control Interface
DS CS R/W A5/
A0
DTA D7/
D0
CSTo
Figure 1 - Functional Block Diagram
2-3
MT8980D
NC
STi2
STi1
STi0
DTA
CSTo
ODE
STo0
STo1
STo2
NC
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
NC
A3
A4
A5
DS
R/W
CS
D7
D6
D5
NC
DTA
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
R/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CSTo
ODE
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
D5
D6
D7
CS
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
44 PIN PLCC
40 PIN PLASTIC DIP
Figure 2 - Pin Connections
Pin Description
Pin #
40
DIP
44
PLCC
Name
Description
1
2
DTA
Data Acknowledgement (Open Drain Output).
This is the data acknowledgement on the
microprocessor interface. This pin is pulled low to signal that the chip has processed the
data. A 909
Ω,
1/4W, resistor is recommended to be used as a pullup.
2-4
5-9
10
11
3-5
7-11
12
13
STi0-
ST-BUS Input 0 to 2 (Inputs).
These are the inputs for the 2048 kbit/s ST-BUS input
STi2 streams.
STi3-
ST-BUS Input 3 to 7 (Inputs).
These are the inputs for the 2048 kbit/s ST-BUS input
STi7 streams.
V
DD
F0i
Power Input.
Positive Supply.
Framing 0-Type (Input).
This is the input for the frame synchronization pulse for the
2048 kbit/s ST-BUS streams. A low on this input causes the internal counter to reset on
the next negative transition of C4i.
4.096 MHz Clock (Input).
ST-BUS bit cell boundaries lie on the alternate falling edges of this
clock.
12
13-
15
16-
18
19
20
21
14
15-
17
19-
21
22
23
24
C4i
A0-A2
Address 0 to 2 (Inputs).
These are the inputs for the address lines on the microprocessor
interface.
A3-A5
Address 3 to 5 (Inputs).
These are the inputs for the address lines on the microprocessor
interface.
DS
R/W
CS
Data Strobe (Input).
This is the input for the active high data strobe on the microprocessor
interface.
Read or Write (Input).
This is the input for the read/write signal on the microprocessor
interface - high for read, low for write.
Chip Select (Input).
This is the input for the active low chip select on the microprocessor
interface
2-4
MT8980D
Pin Description (continued)
Pin #
40
DIP
44
PLCC
Name
Description
22-
24
25-
29
30
31-
35
36-
38
39
25-
27
29-
33
34
35-
39
41-
43
44
D7-D5
Data 7 to 5 (Three-state I/O Pins).
These are the bidirectional data pins on the
microprocessor interface.
D4-D0
Data 4 to 0 (Three-state I/O Pins).
These are the bidirectional data pins on the
microprocessor interface.
V
SS
Power Input.
Negative Supply (Ground).
STo7-
ST-BUS Output 7 to 3 (Three-state Outputs).
These are the pins for the eight 2048
STo3 kbit/s ST-BUS output streams.
STo2-
ST-BUS Output 2 to 0 (Three-state Outputs).
These are the pins for the eight 2048
STo0 kbit/s ST-BUS output streams.
ODE
Output Drive Enable (Input).
If this input is held high, the STo0-STo7 output drivers function
normally. If this input is low, the STo0-STo7 output drivers go into their high impedance state.
NB:
Even when ODE is high, channels on the STo0-STo7 outputs can go high impedance
under software control.
CSTo
Control ST-BUS Output (Complementary Output).
Each frame of 256 bits on this ST-BUS
output contains the values of bit 1 in the 256 locations of the Connection Memory High.
NC
No Connection.
40
1
6, 18,
28,
40
2-5
MT8980D
Functional Description
In recent years, there has been a trend in telephony
towards digital switching, particularly in association
with software control. Simultaneously, there has
been a trend in system architectures towards
distributed processing or multi-processor systems.
In accordance with these trends, MITEL has devised
the ST-BUS (Serial Telecom Bus).
This bus
architecture can be used both in software-controlled
digital voice and data switching, and for
interprocessor communications.
The uses in
switching and in interprocessor communications are
completely integrated to allow for a simple general
purpose architecture appropriate for the systems of
the future.
The serial streams of the ST-BUS operate
continuously at 2048 kbit/s and are arranged in 125
µs
wide frames which contain 32 8-bit channels.
MITEL manufactures a number of devices which
interface to the ST-BUS; a key device being the
MT8980 chip.
The MT8980 can switch data from channels on ST-
BUS inputs to channels on ST-BUS outputs, and
simultaneously allows its controlling microprocessor
to read channels on ST-BUS inputs or write to
channels on ST-BUS outputs (Message Mode). To
the microprocessor, the MT8980 looks like a memory
peripheral. The microprocessor can write to the
MT8980 to establish switched connections between
input ST-BUS channels and output ST-BUS
channels, or to transmit messages on output ST-BUS
channels.
By reading from the MT8980, the
microprocessor can receive messages from ST-BUS
input channels or check which switched connections
have already been established.
By integrating both switching and interprocessor
communications, the MT8980 allows systems to use
distributed processing and to switch voice or data in
an ST-BUS architecture.
A5
0
1
1
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1
A4
X
0
0
•
•
•
1
A3
X
0
0
•
•
•
1
A2
X
0
0
•
•
•
1
A1
X
0
0
•
•
•
1
A0
X
0
1
•
•
•
1
Hardware Description
Serial data at 2048 kbit/s is received at the eight ST-
BUS inputs (STi0 to STi7), and serial data is
transmitted at the eight ST-BUS outputs (STo0 to
STo7). Each serial input accepts 32 channels of
digital data, each channel containing an 8-bit word
which may represent a PCM-encoded analog/voice
sample as provided by a codec (e.g., MITEL’s
MT8964).
This serial input word is converted into parallel data
and stored in the 256 X 8 Data Memory. Locations in
the Data Memory are associated with particular
channels on particular ST-BUS input streams. These
locations can be read by the microprocessor which
controls the chip.
Locations in the Connection Memory, which is split
into high and low parts, are associated with
particular ST-BUS output streams. When a channel
is due to be transmitted on an ST-BUS output, the
data for the channel can either be switched from an
ST-BUS input or it can originate from the
microprocessor. If the data is switched from an
input, then the contents of the Connection Memory
Low location associated with the output channel is
used to address the Data Memory. This Data
Memory address corresponds to the channel on the
input ST-BUS stream on which the data for switching
arrived. If the data for the output channel originates
from the microprocessor (Message Mode), then the
contents of the Connection Memory Low location
associated with the output channel are output
directly, and this data is output repetitively on the
channel once every frame until the microprocessor
intervenes.
The Connection Memory data is received, via the
Control Interface, at D7 to D0. The Control Interface
also receives address information at A5 to A0 and
handles the microprocessor control signals CS,
DTA, R/W and DS. There are two parts to any
address in the Data Memory or Connection Memory.
LOCATION
Control Register *
Channel 0
†
Channel 1
†
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Channel 31
†
HEX ADDRESS
00 - 1F
20
21
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•
3F
* Writing to the Control Register is the only fast transaction.
†
Memory and stream are specified by the contents of the Control Register.
Figure 3- Address Memory Map
2-6
MT8980D
The higher order bits come from the Control
Register, which may be written to or read from via
the Control Interface. The lower order bits come
from the address lines directly.
The Control Register also allows the chip to
broadcast messages on all ST-BUS outputs (i.e., to
put every channel into Message Mode), or to split the
memory so that reads are from the Data Memory
and writes are to the Connection Memory Low. The
Connection Memory High determines whether
individual output channels are in Message Mode,
and allows individual output channels to go into a
high-impedance state, which enables arrays of
MT8980s to be constructed. It also controls the
CSTo pin.
All ST-BUS timing is
signals C4i and F0i.
Software Control
The address lines on the Control Interface give
access to the Control Register directly or, depending
on the contents of the Control Register, to the High
or Low sections of the Connection Memory or to the
Data Memory.
(unused)
Mode
Control
Bits
Memory
Select
Bits
Stream
Address
Bits
If address line A5 is low, then the Control Register is
addressed regardless of the other address lines (see
Fig. 3). If A5 is high, then the address lines A4-A0
select the memory location corresponding to channel
0-31 for the memory and stream selected in the
Control Register.
The data in the Control Register consists of mode
control bits, memory select bits, and stream address
bits (see Fig. 4). The memory select bits allow the
Connection Memory High or Low or the Data
Memory to be chosen, and the stream address bits
define one of the ST-BUS input or output streams.
Bit 7 of the Control Register allows split memory
operation - reads are from the Data Memory and
writes are to the Connection Memory Low.
The other mode control bit, bit 6, puts every output
channel on every output stream into active Message
Mode; i.e., the contents of the Connection Memory
Low are output on the ST-BUS output streams once
every frame unless the ODE pin is low. In this mode
the chip behaves as if bits 2 and 0 of every
Connection Memory High location were 1,
regardless of the actual values.
derived from the two
7
6
5
4
3
2
1
0
BIT
7
NAME
Split
Memory
DESCRIPTION
When 1, all subsequent reads are from the Data Memory and writes are to the Connection
Memory Low, except when the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In either case, the Stream
Address Bits select the subsection of the memory which is made available.
When 1, the contents of the Connection Memory Low are output on the Serial Output
streams except when the ODE pin is low. When 0, the Connection Memory bits for each
channel determine what is output.
6
Message
Mode
(unused)
5
4-3
Memory
0-0 - Not to be used
Select Bits
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
Stream
Address
Bits
The number expressed in binary notation on these bits refers to the input or output ST-BUS
stream which corresponds to the subsection of memory made accessible for subsequent
operations.
Figure 4 - Control Register Bits
2-7
2-0
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