FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
December 1999
FM93C56
2K-Bit Serial CMOS EEPROM
(MICROWIRE™ Bus Interface)
General Description
The FM93C56 device is 2048 bits of CMOS non-volatile electri-
cally erasable memory organized as 128x16 bit array. They are
fabricated using Fairchild Semiconductor's floating-gate CMOS
process for high reliability, high endurance and low power con-
sumption. These memory devices are available in an 8-pin SOIC
or 8-pin TSSOP package for small space considerations.
FM93C56 is compatible with MICROWIRE serial interface, which
offers simple interface to standard microcontrollers and micropro-
cessors. There are 7 instructions which control this device: Read,
Write Enable, Erase, Erase All, Write, Write All, and Write Disable.
The ready/busy status is available on the DO pin to indicate the
completion of a programming cycle.
Features
I
Device status during programming mode
I
Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I
No erase required before write
I
Reliable CMOS floating gate technology
I
2.7V to 5.5V operation in all modes
I
MICROWIRE compatible serial l/O
I
Self-timed programming cycle
I
40 years data retention
I
Endurance: 1,000,000 data changes
I
Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
I
Schmitt Trigger inputs and V
CC
lockout to prevent data
corruption
Block Diagram
CS
SK
DI
INSTRUCTION
REGISTER
V
CC
INSTRUCTION
DECODER
CONTROL LOGIC,
AND CLOCK
GENERATORS
ADDRESS
REGISTER
V
PP
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
DECODER
1 OF 128
EEPROM ARRAY
16
READ/WRITE AMPS
16
V
SS
DATA IN/OUT REGISTER
16 BITS
DO
DATA OUT BUFFER
DS800026-1
© 1999 Fairchild Semiconductor Corporation
FM93C56
1
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Connection Diagrams
Dual-In-Line Package (N),
8-Pin SO (M8) and 8-Pin TSSOP (MT8)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
V
CC
NC
NC
GND
DS800026-2
Rotated Die (93C56T)
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
NC
GND
DO
DI
DS800026-12
Top View
See Package Number
N08E, M08A and MTC08
Pin Names
CS
SK
DI
DO
GND
V
CC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Ordering Information
FM
93
C
XX
T
LZ
E
XX
Package
Letter
N
M8
MT8
None
V
E
Blank
L
LZ
Blank
T
Density
56
C
CS
Interface
93
FM
Description
8-Pin DIP
8-Pin SO8
8-Pin TSSOP
0 to 70°C
-40 to +125°C
-40 to +85°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
Normal Pin Out
Rotated Die Pin Out
2K
CMOS
Data protect and sequential
read
MICROWIRE
Fairchild Non-Volatile
Memory
Temp. Range
Voltage Operating Range
2
FM93C56
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltage
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
ESD Rating
–65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Operating Range
Ambient Operating Temperature
FM93C56
FM93C56E
FM93C56V
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4.5V to 5.5V
DC and AC Electrical Characteristics
4.5V
≤
V
CC
≤
5.5V
Symbol
I
CCA
I
CCS
I
IL
I
OL
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
f
SK
t
SKH
t
SKL
t
SKS
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
Part Number
Conditions
CS = V
IH
, SK = 1MHz
CS = V
IL
V
IN
= 0V to V
CC
(Note 2)
Min.
Max.
1
50
±1
Units
mA
µA
µA
V
V
V
V
V
MHz
ns
ns
ns
-0.1
2
I
OL
= 2.1mA
I
OH
= -400
µA
I
OL
= 10
µA
I
OH
= -10
µA
(Note 3)
FM93C56
FM93C56E/V
SK must be at V
IL
for
t
SKS
before CS goes
high
(Note 4)
2.4
0.8
V
CC
+1
0.4
0.2
V
CC
-0.2
0
250
300
250
50
1
t
CS
t
CSS
t
DH
t
DIS
t
CSH
t
DIH
t
PD
t
SV
t
DF
t
WP
Minimum CS
Low Time
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
FM93C56
FM93C56E/V
250
50
70
100
200
0
20
500
500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
CS = V
IL
100
10
3
FM93C56
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltage
with Respect to Ground
Lead Temperature (Soldering, 10 sec.)
ESD Rating
–65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Operating Range
Ambient Operating Temperature
FM93C56L/LZ
FM93C56LE/LZE
FM93C56LV/LZV
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V to 5.5V
DC and AC Electrical Characteristics
V
CC
= 2.7V to 5.5V unless otherwise specified
Symbol
I
CCA
I
CCS
Parameter
Operating Current
Standby Current
L
LZ
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
Part Number
Conditions
CS = V
IH
, SK = 250KHz
CS = V
IL
Min.
Max.
1
10
1
Units
mA
µA
µA
µA
V
V
V
KHz
µs
µs
µs
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
SK
t
SKH
t
SKL
t
SKS
V
IN
= 0V to V
CC
(Note 2)
-0.1
0.8 V
CC
I
OL
= 10
µA
I
OH
= -10
µA
(Note 3)
0.9 V
CC
0
1
1
SK must be at V
IL
for
t
SKS
before CS goes
high
(Note 4)
0.2
±1
0.15 V
CC
V
CC
+1
0.1 V
CC
250
t
CS
t
CSS
t
DH
t
DIS
t
CSH
t
DIH
t
PD
t
SV
t
DF
t
WP
Minimum CS
Low Time
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
1
0.2
70
0.4
0
0.4
2
1
µs
µs
ns
µs
ns
µs
µs
µs
µs
ms
CS = V
IL
0.4
15
Capacitance
T
A
= 25°C, f = 1 MHz (Note 5)
Symbol
C
OUT
C
IN
Note 1:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Test
Output Capacitance
Input Capacitance
Typ
Max
5
5
Units
pF
pF
Note 3:
The shortest allowable SK clock period = 1/f
SK
(as shown under the f
SK
parameter).
Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC
parameters stated in the datasheet. Within this SK period, both t
SKH
and t
SKL
limits must be observed.
Therefore, it is not allowable to set 1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 4:
CS (Chip Select) must be brought low (to V
IL
) for an interval of t
CS
in order to reset all
internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the
opcode diagram on the following page.)
Note 5:
This parameter is periodically sampled and not 100% tested.
AC Test Conditions
V
CC
Range
2.7V
≤
V
CC
≤
5.5V
(Extended Voltage Levels)
V
IL
/V
IH
Input Levels
.03V/1.8V
0.4V/2.4V
V
IL
/V
IH
Timing Level
1.0V
1.0V/2.0V
V
OL
/V
OH
Timing Level
0.8V/1.5V
0.4V/2.4V
I
OL
/I
OH
±10µA
2.1mA/-0.4mA
4.5V
≤
V
CC
≤
5.5V
(TTL Levels)
Output Load: 1 TTL Gate (C
L
= 100 pF)
4
FM93C56
www.fairchildsemi.com
FM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE™ Bus Interface)
Functional Description
The FM93C56 device has 7 instructions as described below. Note
that the MSB of any instruction is a “1” and is viewed as a start bit
in the interface sequence. The next 10 bits carry the op code and
the 8-bit address for register selection.
Write (WRITE):
The WRITE instruction is followed by the address and 16 bits of data
to be written into the specified address. After the last bit of data is
put in the data-in (DI) pin, CS must be brought low before the next
rising edge of the SK clock. This falling edge of the CS initiates the
self-timed programming cycle. The D0 pin indicates the READY/
BUSY status of the chip if CS is brought high after a minimum of t
CS
.
D0 = logical 1 indicates that the register at the address specified in
the instruction has been written with the data pattern specified in the
instruction and the part is ready for another instruction.
Read (READ):
The READ instruction outputs serial data on the D0 pin. After a
READ instruction is received, the instruction and address are
decoded, followed by data transfer from the selected memory
register into a 16-bit serial-out shift register. A dummy bit (logical
0) precedes the 16-bit data output string. Output data changes are
initiated by a low to high transition of the SK clock.
Erase All (ERAL):
The ERAL instruction will simultaneously program all registers in
the memory array and set each bit to the logical “1” state. The Erase
All cycle is identical to the ERASE cycle except for the different op-
code. As in the ERASE mode, the DO pin indicates the READY/
BUSY status of the chip if CS is brought high after the t
CS
interval.
Write Enable (WEN):
When V
CC
is applied to the part, it 'powers-up' in the Write Disable
(WDS) state. Therefore, all programming modes must be pre-
ceded by a Write Enable (WEN) instruction. Once a Write Enable
instruction is executed, programming remains enabled until aWrite
Disable (WDS) instruction is executed or V
CC
is removed from the
part.
Write All (WRALL):
The WRALL instruction will simultaneously program all registers
with the data pattern specified in the instruction. As in the WRITE
mode, the DO pin indicates the READY/BUSY status of the chip
if CS is brought high after the t
CS
interval.
Erase (ERASE):
The ERASE instruction will program all bits in the specified
register to the logical “1” state. CS is brought low following the
loading of the last address bit. This falling edge of the CS pin
initiates the self-timed programming cycle.
The DO pin indicates the READY/BUSY status of the chip if CS is
brought high after a minimum time of t
CS
. DO = logical “0” indicates
that the register, at the address specified in the instruction, has
been erased, and the part is ready for another instruction.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruction
disables all programming modes and should follow all program-
ming operations. Execution of a READ instruction is independent
of both the WEN and WDS instructions.
Note:
The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"
operation prior to the "WRITE" and "WRITE ALL" instructions. The "ERASE" and "ERASE
ALL" instructions are included to maintain compatibility with earlier technology EEPROMs.
Instruction Set for the FM93C56
Instruction
READ
WEN
ERASE
WRITE
ERAL
WRALL
WDS
Note:
Note:
SB
1
1
1
1
1
1
1
Op. Code
10
00
11
01
00
00
00
Address
A7-A0
11xxxxxx
A7-A0
A7-A0
10xxxxxx
01xxxxxx
00xxxxxx
Data
Comments
Reads data stored in memory, at specified address.
Write enable must precede all programming modes.
Erase selected register.
D15-D0
D15-D0
Writes selected register.
Erases all registers.
Writes all registers.
Disables all programming instructions.
A7 is "don't care" bit, but must be included in the address string.
x = Don't care.
5
FM93C56
www.fairchildsemi.com
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