GS840H18/32/36T/B-180/166/150/100
TQFP, BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user configurable flow through or pipelined operation.
• Single Cycle Deselect (SCD) Operation.
• High Output Drive current.
• 3.3V +10%/-5% Core power supply
• 2.5V or 3.3V I/O supply.
• LBO pin for linear or interleaved burst mode.
• Internal input resistors on mode pins allow floating mode pins.
• Default to Interleaved Pipelined Mode.
• Byte write (BW) and/or global write (GW) operation.
• Common data inputs and data outputs.
• Clock Control, registered, address, data, and control.
• Internal Self-Timed Write cycle.
• Automatic power-down for portable applications.
• JEDEC standard 100-lead TQFP or 119 Bump BGA package.
-180
5.5ns
3.2ns
330mA
8ns
10ns
190mA
-166
6.0ns
3.5ns
310mA
8.5ns
10ns
190mA
-150
6.6ns
3.8ns
275mA
10ns
10ns
190mA
-100
10ns
4.5ns
190mA
12ns
15ns
140mA
256K x 18, 128K x 32, 128K x 36
4Mb Sync Burst SRAMs
Flow Through / Pipeline Reads
180Mhz - 100Mhz
3.3V VDD
3.3V & 2.5V I/O
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
The function of the Data Output register can be controlled by the user
via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the
BGA, ). Holding the FT mode pin/bump low places the RAM in Flow
through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipelined Mode,
activating the rising edge triggered Data Output Register.
SCD Pipelined Reads
The GS840H18/32/36 is an SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available.SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tCycle
t
KQ
I
DD
t
KQ
tCycle
I
DD
Byte Write and Global Write
Byte write operation is performed by using byte write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Functional Description
Applications
The GS840H18/32/36 is a 4,718,592 bit (4,194,304 bit for x32
version) high performance synchronous SRAM with a 2 bit burst
address counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPU’s, the device
now finds application in synchronous SRAM applications ranging from
DSP main store to networking chip set support. The GS840H18/32/36
is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA
package.
Core and Interface Voltages
The GS840H18/32/36 operates on a 3.3V power supply and all
inputs/outputs are 3.3V and 2.5V compatible. Separate output power
(V
DDQ
) pins are used to de-couple output noise from the internal
circuit.
Controls
Addresses, data I/O’s, chip enables (E
1
, E
2
, E
3
), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive edge triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
Rev: 2.04 6/2000
1/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS840H18/32/36T/B-180/166/150/100
GS840H18 100 Pin TQFP Pinout
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
FT
V
DD
NC
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
NC
V
SS
V
DDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
NC
NC
B
B
B
A
E
3
V
DD
V
SS
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
A
17
NC
NC
V
DDQ
V
SS
NC
DQ
A9
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
NC
NC
V
SS
V
DDQ
NC
NC
NC
Rev: 2.04 6/2000
LBO
A
5
A
4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
2/31
© 1999, Giga Semiconductor, Inc.
GS840H18/32/36T/B-180/166/150/100
GS840H32 100 Pin TQFP Pinout
NC
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
128K x 32
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
NC
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
NC
Rev: 2.04 6/2000
LBO
A
5
A
4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
3/31
© 1999, Giga Semiconductor, Inc.
GS840H18/32/36T/B-180/166/150/100
GS840H36 100 Pin TQFP Pinout
DQ
C9
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
FT
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
DQ
D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
128K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
DQ
B9
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
DQ
A9
Rev: 2.04 6/2000
LBO
A
5
A
4
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
A
16
4/31
© 1999, Giga Semiconductor, Inc.
GS840H18/32/36T/B-180/166/150/100
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46,
47, 48, 49, 50
80
52, 53, 56, 57, 58, 59, 62, 63
68, 69, 72, 73, 74, 75, 78, 79
2, 3, 6, 7, 8, 9, 12, 13
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
51, 80, 1, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79
1, 2, 3, 6, 7
25, 28, 29, 30
87
93, 94
95, 96
95, 96
89
88
98, 92
97
86
83
84, 85
64
14
31
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
16, 38, 39, 42, 43, 66
Symbol
A
0
, A
1
A
2
-
16
A
17
DQ
A1
-DQ
A8
DQ
B1
-DQ
B8
DQ
C1
-DQ
C8
DQ
D1
-DQ
D8
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
NC
DQ
A1
-DQ
A9
DQ
B1
-DQ
B9
NC
BW
B
A
, B
B
B
C
, B
D
NC
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
FT
LBO
V
DD
V
SS
V
DDQ
NC
Type
I
I
I
I/O
Description
Address field LSB’s and Address Counter preset Inputs
Address Inputs
Address Inputs (x18 versions)
Data Input and Output pins. (x32, x36 Version)
I/O
Data Input and Output pins. (x36 Version)
No Connect (x32 Version)
I/O
Data Input and Output pins. (x18 Version)
-
I
I
I
-
I
I
I
I
I
I
I
I
I
I
I
I
I
-
No Connect (x18 Version)
Byte Write. Writes all enabled bytes. Active Low.
Byte Write Enable for DQ
A
, DQ
B
Data I/O’s. Active Low.
Byte Write Enable for DQ
C
, DQ
D
Data I/O’s. Active Low.
(x32, x36 Version)
No Connect (x18 Version)
Clock Input Signal. Active High.
Global Write Enable. Writes all bytes. Active Low.
Chip Enable. Active Low.
Chip Enable. Active High.
Output Enable. Active Low.
Burst address counter advance enable. Active Low.
Address Strobe (Processor, Cache Controller). Active Low.
Sleep Mode control. Active High.
Flow Through or Pipeline mode. Active Low.
Linear Burst Order mode. Active Low.
Core power supply.
I/O and Core Ground.
Output driver power supply.
No Connect.
Rev: 2.04 6/2000
5/31
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
FPGA/CPLD
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