The PEEL™22CV10AZ is a Programmable Electrically Erasable
Logic (PEEL™) device that provides a low power alternative to
ordinary PLDs. The PEEL™22CV10AZ is available in 24-pin
DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 19). A
“zero-power” (100µA max. I
CC
) standby mode makes the
PEEL™22CV10AZ ideal for power sensitive applications such as
handheld meters, portable communication equipment and lap- top
computers/ peripherals. EE-reprogrammability provides the
convenience of instant reprogramming for development and a
reusable production inventory minimizing the impact of pro-
gramming changes or errors. EE-reprogrammability also
improves factory testability, thus ensuring the highest quality
possible.
The PEEL™22CV10AZ is JEDEC file compatible with standard
22V10 PLDs. Eight additional configurations per macrocell (a
total of 12) are also available by using the “+” software/program-
ming option (i.e., 22CV10AZ+ & 22CV10AZ++). The additional
macrocell configurations allow more logic to be put into every
device, potentially reducing the design's component count and
lowering the power requirements even further.
Development
and
programming
support
for
the
PEEL™22CV10AZ is provided by popular third-party program-
mers and development software. Anachip also offers free Win-
PLACE development software.
Figure 19 Block Diagram
Figure 19 Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
DIP
TSSOP
PLCC
SOIC
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10
Figure 21 PEEL™22CV10AZ Logic Array Diagram
Anachip Corp.
www.anachip.com.tw
2/10
Rev. 1.0 Dec 16, 2004
Function Description
The implements logic functions as sum-of-products expressions in
a programmable-AND/fixed-OR logic array. User-defined
functions are created by programming the connections of input
signals into the array. User-configurable output structures in the
form of I/O macrocells further increase logic flexibility.
Architecture Overview
The architecture is illustrated in the block diagram of Figure 19.
Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and
10 outputs for creating logic functions (see Figure 21). At the
core of the device is a programmable electrically-erasable AND
array that drives a fixed OR array. With this structure, the
PEEL™22CV10AZ can implement up to 10 sum-of-products
logic expressions.
Associated with each of the ten OR functions is an I/O macrocell
that can be independently programmed to one of four different
configurations in standard 22V10 mode, or any one of 12 config-
urations using the special “Plus” mode. The programmable mac-
rocells allow each I/O to be used to create sequential or
combinatorial logic functions of active-high or active-low polar-
ity, while providing three different feedback paths into the AND
array.
grammer first performs a bulk erase to remove the previous pat-
tern. The erase cycle opens every logical connection in the array.
The device is configured to perform the user-defined function by
programming selected connections in the AND array. (Note that
PEEL™ device programmers automatically program all of the
connections on unused product terms so that they will have no
effect on the output function).
Variable Product Term Distribution
The PEEL™22CV10AZ provides 120 product terms to drive the
10 OR functions. These product terms are distributed among the
outputs in groups of 8, 10, 12, 14, and 16 to form logical sums
(see Figure 21). This distribution allows optimum use of the
device resources.
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides com-
plete control over the architecture of each output. The ability to
configure each output independently lets you to tailor the config-
uration of the PEEL™22CV10AZ to the precise requirements of
your design.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 20, consists of a D-type
flip-flop and two signal-select multiplexers. The configuration of
the macrocell is determined by four EEPROM bits that control the
multiplexers. These bits determine the output polarity, output type
(registered or non-registered) and input-feedback path (bidi-
rectional I/O, combinatorial feedback). Refer to Table 1. for
details. Four of these macrocells duplicate the functionality of the
industry-standard PAL22V10. (See Figure 21 and Table 1.)
AND/OR Logic Array
The programmable AND array of the PEEL™22CV10AZ
(shown in Figure 21) is formed by input lines intersecting prod- uct
terms. The input lines and product terms are used as follows:
44 Input Lines:
– 24 input lines carry the true and complement of the signals
applied to the 12 input pins
– 20 additional lines carry the true and complement values of
feedback or input signals from the 10 I/Os
133 Product Terms:
– 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and
16) are used to form sum of product functions
– 10 output enable terms (one for each I/O)
– 1 global synchronous preset term
– 1 global asynchronous clear term
– 1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not there is a
logical connection at that intersection. Each product term is
essentially a 44-input AND gate. A product term that is con-
nected to both the true and complement of an input signal will
always be FALSE and therefore will not affect the OR function
that it drives. When all the connections on a product term are
opened, a “don’t care” state exists and that term will always be
TRUE.
Figure 20 Block Diagram of the
PEEL™22CV10A I/O Macrocell
When programming the PEEL™22CV10AZ, the device pro-
Anachip Corp.
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3/10
Rev. 1.0 Dec 16, 2004
In addition to emulating the four PAL-type output structures
(configurations 3, 4, 9, and 10), The macrocell provides eight
additional configurations. Equivalent circuits for the twelve mac-
rocell configurations are illustrated in Figure 22. These structures
are accessed by specifying the PEEL™22CV10A+ or
PEEL™22CV10A++ option when assembling the equations.
Output Polarity
Each macrocell can be configured to implement active-high or
active-low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled
under the control of its associated programmable output enable
product term. When the logical conditions programmed on the
output enable term are satisfied, the output signal is propagated to
the I/O pin. Otherwise, the output buffer is switched into the
high-impedance state.
Under the control of the output enable term, the I/O pin can func-
tion as a dedicated input, a dedicated output, or a bi-directional I/ O.
Opening every connection on the output enable term will per-
manently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will
always be logically false and the I/O will function as a dedicated
input.
Figure 21 Equivalent Circuits for the Four Con-
figurations of the I/O Macrocell
Input/Feedback Select
When configuring an I/O macrocell to implement a registered
function (configurations 1 and 2 in Figure 21), the Q output of the
flip-flop drives the feedback term. When configuring an I/O mac-
rocell to implement a combinatorial output (configurations 3 and
4 in Figure 21), the feedback term is taken from the I/O pin. In this
case, the pin can be used as a dedicated input or a bi-direc- tional
I/O (Refer also to Table 1.)
Table 1. PEEL™22CV10A Macrocell
Configuration Bits
Configuration
#
1
2
3
4
Input/Feedback
Select
Register
Feedback
Bi-Directional
I/O
Combinatorial
Register
A
0
1
0
B
0
0
1
Output Select
Active Low
Active High
Active Low
Active High
Programmable Clock Options
A unique feature of the PEEL™22CV10AZ is a programmable
clock multiplexer that allows you to select true or complement
forms of either the input pin or a product-term clock source. This
feature can be accessed by specifying the PEEL™22CV10A++
option when assembling the equations.
When creating a PEEL™ device design, the desired macrocell
configuration is generally specified explicitly in the design file.
When the design is assembled or compiled, the macrocell config-
uration bits are defined in the last lines of the JEDEC program-
ming file.
Output Type
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (regis-
tered function). The D-type flip-flop latches data on the rising
edge of the clock and is controlled by the global preset and clear
terms. When the synchronous preset term is satisfied, the Q out-
put of the register is set HIGH at the next rising edge of the clock
input. Satisfying the asynchronous clear sets Q LOW, regardless of
the clock state. If both terms are satisfied simultaneously, the clear
will override the preset.
Anachip Corp.
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4/10
Rev. 1.0 Dec 16, 2004
Figure 22 Equivalent Circuits for the Twelve Configurations of the PEEL™22CV10AZ+ I/O Macrocell
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