Preliminary
HY27US(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1Gb NAND FLASH
HY27US081G1M
HY27US161G1M
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.2 / May. 2007
1
Preliminary
HY27US(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Document Title
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.01
Initial Draft.
1) Delete PRE pin.
0.02
2) Delete Lock mechanism.
3) Delete FBGA Package.
- Figure & dimension are changed.
1) Change DC characteristics (Table 8)
I
CC1
0.03
Before
After
Typ
15
10
Max
30
20
I
CC2
Typ
15
10
Max
30
20
I
CC3
Typ
15
10
Max
30
20
Dec. 14. 2005
Preliminary
Dec. 01. 2005
Preliminary
History
Draft Date
Nov. 11. 2005
Remark
Preliminary
1) Add ECC algorithm. (1bit/512bytes)
0.04
2) Correct Read ID Cycle & Read ID naming
3) Correct Copy back program
4) Change DC and Operating Characteristics
1) Correct Read ID Cycle
0.1
0.2
2) Change NOP
3) Correct copy back function
1) Correct figure 32.
May. 18. 2007
Preliminary
Oct. 02. 2006
Preliminary
Mar. 28. 2006
Preliminary
Rev 0.2 / May. 2007
2
Preliminary
HY27US(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle : Manufacturer Code
- 2nd cycle : Device Code
SUPPLY VOLTAGE
- VCC = 2.7 to 3.6V : HY27USxx1G1M
Memory Cell Array
= (512+16) Bytes x 32 Pages x 8,192 Blocks
= (256+8) Words x 32 Pages x 8,192 Blocks
PAGE SIZE
- x8 device : (512 + 16 spare) Bytes
: HY27US081G1M
- x16 device : (256+ 8 spare) Words
: HY27US161G1M
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles (with 4bit/528byte ECC)
- 10 years Data Retention
PACKAGE
- HY27US(08/16)1G1M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27US(08/16)1G1M-T (Lead)
- HY27US(08/16)1G1M-TP (Lead Free)
- HY27US081G1M-S(P)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27US081G1M-S (Lead)
- HY27US081G1M-SP (Lead Free)
CHIP ENABLE DON’T CARE OPTION
- Simple interface with microcontroller
- 3rd cycle: Internal chip number, Cell Type, Number of
Simultaneously Programmed Pages.
- 4th cycle: Page size, Block size, Organization, Spare
size
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words
PAGE READ / PROGRAM
- Random access: 15us (max.)
- Sequential access: 50ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
Rev 0.2 / May. 2007
3
Preliminary
HY27US(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27US(08/16)1G1M series is a 128Mx8bit with spare 4Mx8 bit capacity. The device is offered in 3.3V Vcc
Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 8192 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected
Flash cells.
A program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 16Kbyte(X8 device) block.
Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27US(08/16)1G1M extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE don’t care function. This option allows the direct download of the code
from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The HYNIX HY27US(08/16)1G1M series is available in 48 - TSOP1 12x20 mm, 48 - USOP1 12 x 17 mm.
1.1 Product List
PART NUMBER
HY27US081G1M
HY27US161G1M
ORIZATION
x8
x16
VCC RANGE
2.7V - 3.6 Volt
PACKAGE
48TSOP1 / 48USOP1
Rev 0.2 / May. 2007
4
Preliminary
HY27US(08/16)1G1M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Figure1: Logic Diagram
IO15 - IO8
IO7 - IO0
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
NC
Data Inputs / Outputs (x16 Only)
Data Inputs / Outputs
Command latch enable
Address latch enable
Chip Enable
Read Enable
Write Enable
Write Protect
Ready / Busy
Power Supply
Ground
No Connection
Table 1: Signal Names
Rev 0.2 / May. 2007
5
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