FUJITSU SEMICONDUCTOR
DATA SHEET
DS07–12627–7E
8-bit Microcontrollers
CMOS
New 8FX MB95260H/270H/280H Series
MB95F262H/F262K/F263H/F263K/F264H/F264K
MB95F272H/F272K/F273H/F273K/F274H/F274K
MB95F282H/F282K/F283H/F283K/F284H/F284K
■
DESCRIPTION
MB95260H/270H/280H are series of general-purpose, single-chip microcontrollers. In addition to a compact
instruction set, the microcontrollers of these series contain a variety of peripheral resources.
■
FEATURES
• F
2
MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
Note: F
2
MC is the abbreviation of FUJITSU Flexible Microcontroller.
• Clock (main OSC clock and sub-OSC clock are only available on MB95F262H/F262K/F263H/F263K/F264H/
F264K/F282H/F282K/F283H/F283K/F284H/F284K)
• Selectable main clock source
Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main CR clock (1/8/10 MHz
±3%,
maximum machine clock frequency: 10 MHz)
• Selectable subclock source
Sub-OSC clock (32.768 kHz)
External clock (32.768 kHz)
Sub CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
• Timer
• 8/16-bit composite timer
• Time-base timer
• Watch prescaler
• LIN-UART (only available on MB95F262H/F262K/F263H/F263K/F264H/F264K/F282H/F282K/F283H/
F283K/F284H/F284K)
• Full duplex double buffer
• Capable of clock-synchronized serial data transfer and clock-asynchronized serial data transfer
(Continued)
Copyright©2008-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.6
MB95260H/270H/280H Series
(Continued)
• External interrupt
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter
• 8-bit or 10-bit resolution can be selected.
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port (Max: 17) (MB95F262K/F263K/F264K)
• General-purpose I/O ports (Max):
CMOS I/O: 15, N-ch open drain: 2
• I/O port (Max: 16) (MB95F262H/F263H/F264H)
• General-purpose I/O ports (Max):
CMOS I/O: 15, N-ch open drain: 1
• I/O port (Max: 5) (MB95F272K/F273K/F274K)
• General-purpose I/O ports (Max):
CMOS I/O: 3, N-ch open drain: 2
• I/O port (Max: 4) (MB95F272H/F273H/F274H)
• General-purpose I/O ports (Max):
CMOS I/O: 3, N-ch open drain: 1
• I/O port (Max: 13) (MB95F282K/F283K/F284K)
• General-purpose I/O ports (Max):
CMOS I/O: 11, N-ch open drain: 2
• I/O port (Max: 12) (MB95F282H/F283H/F284H)
• General-purpose I/O ports (Max):
CMOS I/O: 11, N-ch open drain: 1
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Built-in software watchdog timer
• Power-on reset
• A power-on reset is generated when the power is switched on.
• Low-voltage detection reset circuit
• Built-in low-voltage detector
• Clock supervisor counter
• Built-in clock supervisor counter function
• Programmable port input voltage level
• CMOS input level / hysteresis input level
• Dual operation Flash memory
• The program/erase operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
• Protects the content of the Flash memory
2
DS07–12627–7E
MB95260H/270H/280H Series
■
PRODUCT LINE-UP
• MB95260H Series
Part number
MB95F262H
Parameter
MB95F263H
MB95F264H
MB95F262K
MB95F263K
MB95F264K
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
496 bytes
240 bytes
496 bytes
496 bytes
Power-on reset
Yes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected by software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 16
• I/O ports (Max) : 17
General-
• CMOS I/O
: 15
• CMOS I/O
: 15
purpose I/O
• N-ch open drain: 1
• N-ch open drain: 2
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Hardware/
Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer • The sub CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
• A wide range of communication speed can be selected by a dedicated reload timer.
• It has a full duplex double buffer.
LIN-UART
• Clock-synchronized serial data transfer and clock-asynchronized serial data transfer is en-
abled.
• The LIN function can be used as a LIN master or a LIN slave.
6 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
2 channels
• The timer can be configured as an "8-bit timer
×
2 channels" or a "16-bit timer
×
1 channel".
8/16-bit
composite timer • It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
6 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing. (asynchronous mode)
(Continued)
DS07–12627–7E
3
MB95260H/270H/280H Series
(Continued)
Part number
MB95F262H
Parameter
MB95F263H
MB95F264H
MB95F262K
MB95F263K
MB95F264K
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory
• Number of program/erase cycles: 100000
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
DIP-24P-M07
LCC-32P-M19
Package
FPT-20P-M09
FPT-20P-M10
4
DS07–12627–7E
MB95260H/270H/280H Series
• MB95270H Series
Part number
MB95F272H
Parameter
MB95F273H
MB95F274H
MB95F272K
MB95F273K
MB95F274K
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
496 bytes
240 bytes
496 bytes
496 bytes
Power-on reset
Yes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected by software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 5
• I/O ports (Max) : 4
General-
• CMOS I/O
:3
• CMOS I/O
:3
purpose I/O
• N-ch open drain: 2
• N-ch open drain: 1
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
Hardware/
• Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer • The sub-internal CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
LIN-UART
No LIN-UART
2 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
1 channel
• The timer can be configured as an "8-bit timer
×
2 channels" or a "16-bit timer
×
1 channel".
8/16-bit
composite timer • It has built-in timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave.
2 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from standby modes.
• 1-wire serial control
On-chip debug
• It supports serial writing. (asynchronous mode)
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming, Embedded Algorithm, program/erase/erase-suspend/
erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory
• Number of program/erase cycles: 100000
• Data retention time: 20 years
• Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
Package
DS07–12627–7E
DIP-8P-M03
FPT-8P-M08
5
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