HY5DW113222FM(P)
DESCRIPTION
Preliminary
The Hynix HY5DW113222FM(P) is a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM which consists
of two 256Mbit(x32) - Multi-chip-, ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 16Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
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The Hynix HY5DW113222FM(P) guarantee until
200MHz speed at DLL_off condition
2.5V +/- 5% V
DD
and 1.8V +/- 5% V
DDQ
power
supply
All inputs and outputs are compatible with SSTL_2
interface
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
Fully differential clock inputs (CK, /CK) operation
The signals of Chip select control the each chip with
CS0 and CS1, individually.
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
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Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 5 / 4 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
(Both chips do refresh operation, simultaneously)
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Half strength and Matched Impedance driver option
controlled by EMRS
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ORDERING INFORMATION
Part No.
HY5DW113222FM(P)-2
HY5DW113222FM(P)-22
HY5DW113222FM(P)-25
HY5DW113222FM(P)-28
HY5DW113222FM(P)-33
HY5DW113222FM(P)-36
HY5DW113222FM(P)-4
Power
Supply
Clock
Frequency
500MHz
450MHz
400MHz
350MHz
300MHz
275MHz
250MHz
Max Data Rate
1000Mbps/pin
900Mbps/pin
800Mbps/pin
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
interface
Package
V
DD
2.5V
V
DDQ
1.8V
12mmx12mm
SSTL_2
144Ball FBGA
Note)
Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials.
We'll add "P" character after "FM" for lead free product. For example, the part number of 300MHz Lead free
product is HY5DW113222FM(P) - 33.
Rev. 0.1 / Oct. 2004
3
HY5DW113222FM(P)
PIN DESCRIPTION
PIN
CK, /CK
TYPE
Input
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS0 or CS1 is registered high. CS0 or CS1 provides for external
bank selection on systems with multiple banks. CS0 and CS1 are considered part of the
command code. When it is the operationg state of MRS, Power up sequence, EMRS, it
should be enabled in pairs. Except this case, it can be operated, individually.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A8 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-
pled on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the
data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the
data on DQ24-Q31.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. DQS0 corresponds to the data on
DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on
DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31
Data input / output pin : Data Bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
CKE
Input
/CS0, /CS1
Input
BA0, BA1
Input
A0 ~ A11
Input
/RAS, /CAS, /WE
Input
DM0 ~ DM3
Input
DQS0 ~ DQS3
I/O
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC
I/O
Supply
Supply
Supply
NC
Rev. 0.1 / Oct. 2004
5
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