16Mx72 bits
Unbuffered DDR SO-DIMM
HYMD216726A(L)6J-J
DESCRIPTION
Hynix HYMD216726A(L)6J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory
Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD216726A(L)6J-J series
consists of eighteen 16Mx16 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix
HYMD216726A(L)6J-J series provide a high performance 8-byte interface in 5.25" width form factor of industry stan-
dard. It is suitable for easy interchange and addition.
Hynix HYMD216726A(L)6J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera-
tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD216726A(L)6J-J series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
•
•
•
•
•
•
•
128MB (16M x72) Unbuffered DDR DIMM based on
16Mx16 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
Error Check Correction (ECC) Capability
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz/166MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
•
•
•
•
•
•
•
•
•
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
Data inputs on DQS centers when write (centered
DQ)
Data strobes synchronized with output data for read
and input data for write
Programmable CAS Latency 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD216726A(L)6J-J
Power Supply
V
DD
=2.5V
V
DDQ
=2.5V
Clock Frequency
166MHz (*DDR333)
Interface
SSTL_2
Form Pactor
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2/Jul. 02
1
HYMD216726A(L)6J-J
FUNCTIONAL BLOCK DIAGRAM
/CS0
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LDQS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CS
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
LDQS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CS
D0
DQ43
DQ44
DQ45
DQ46
DQ47
D2
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DM4/DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
LDQS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CS
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
LDQS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CS
D1
DQ59
DQ60
DQ61
DQ62
DQ63
D3
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Serial PD
VCC
100K
NU
NU
NU
NU
NU
NU
NU
NU
100K
LDQS
LDM
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
UDQS
UDM
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/CS
SCL
WP
A0
A1
A2
SA2
SDA
SA0 SA1
D4
*Clock Wiring
Clock Input
*CK0, /CK0
*CK1, /CK1
*CK2, /CK2
SDRAMs
1 SDRAMs
2 SDRAMs
2 SDRAMs
VDD SPD
VDD /VDDQ
SPD
DO-D4
DO-D4
DO-D4
Strap:see Note 4
DQS8
DM8/DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
VREF
VSS
VDDID
*Wire per Clock Loading
Table/Wiring Diagrams
Notes :
BA0-BA1
A0-A13
/RAS
/CAS
CKE0
/WE
BA0-BA1 : SDRAMs D0-D4
A0-A13 : SDRAMs D0-D4
/RAS : SDRAMs D0-D4
/CAS : SDRAMs D0-D4
CKE : SDRAMs D0-D4
/WE : SDRAMs D0-D4
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained
as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms
±
5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ
STRAP IN (VSS) : VDD
≠
V DDQ
5. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms
±
5%
Rev. 0.2/Jul. 02
3
HYMD216726A(L)6J-J
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Voltage on V
DDQ
relative to V
SS
Output Short Circuit Current
Power Dissipation
Soldering Temperature Þ Time
T
A
T
STG
V
IN
, V
OUT
V
DD
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
50
8
260 / 10
Rating
o
o
Unit
C
C
V
V
V
mA
W
o
C / Sec
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Power Supply Voltage
Power Supply Voltage
Input High Voltage
Input Low Voltage
Termination Voltage
Reference Voltage
V
DD
V
DDQ
V
IH
V
IL
V
TT
V
REF
Symbol
Min
2.3
2.3
V
REF
+ 0.15
-0.3
V
REF
- 0.04
1.15
Typ.
2.5
2.5
-
-
V
REF
1.25
Max
2.7
2.7
V
DDQ
+ 0.3
V
REF
- 0.15
V
REF
+ 0.04
1.35
Unit
V
V
V
V
V
V
3
2
1
Note
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CK and /CK inputs
Input Crossing Point Voltage, CK and /CK inputs
Symbol
V
IH(AC)
V
IL(AC)
V
ID(AC)
V
IX(AC)
0.7
0.5*V
DDQ
-0.2
Min
V
REF
+ 0.31
V
REF
- 0.31
V
DDQ
+ 0.6
0.5*V
DDQ
+0.2
Max
Unit
V
V
V
V
1
2
Note
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Rev. 0.2/Jul. 02
4
HYMD216726A(L)6J-J
AC OPERATING TEST CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to VSS = 0V)
Parameter
Reference Voltage
Termination Voltage
AC Input High Level Voltage (V
IH
, min)
AC Input Low Level Voltage (V
IL
, max)
Input Timing Measurement Reference Level Voltage
Output Timing Measurement Reference Level Voltage
Input Signal maximum peak swing
Input minimum Signal Slew Rate
Termination Resistor (R
T
)
Series Resistor (R
S
)
Output Load Capacitance for Access Time Measurement (C
L
)
Value
V
DDQ
x 0.5
V
DDQ
x 0.5
V
REF
+ 0.31
V
REF
- 0.31
V
REF
V
TT
1.5
1
50
25
30
Unit
V
V
V
V
V
V
V
V/ns
W
W
pF
Rev. 0.2/Jul. 02
5
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