SN54HC42, SN74HC42
4 LINE TO 10 LINE DECODERS (1 of 10)
SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
Typical t
pd
= 14 ns
±4-mA
Output Drive at 5 V
SN54HC42 . . . J OR W PACKAGE
SN74HC42 . . . D, N, OR NS PACKAGE
(TOP VIEW)
D
Low Input Current of 1
µA
Max
D
Full Decoding of Input Logic
D
All Outputs Are High for Invalid BCD
D
Conditions
Also for Applications as 3-Line to 8-Line
Decoders
SN54HC42 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
description/ordering information
These decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are connected
in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic
ensures that all inputs remain off for all invalid input conditions.
ORDERING INFORMATION
TA
PDIP − N
PACKAGE†
Tube of 25
Tube of 40
−40°C to 85 C
−40 C 85°C
SOIC − D
SOP − NS
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
Reel of 2500
Reel of 250
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
ORDERABLE
PART NUMBER
SN74HC42N
SN74HC42D
SN74HC42DR
SN74HC42DT
SN74HC42NSR
SNJ54HC42J
SNJ54HC42W
SNJ54HC42FK
HC42
SNJ54HC42J
SNJ54HC42W
SNJ54HC42FK
HC42
TOP-SIDE
MARKING
SN74HC42N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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•
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6
GND
NC
7
8
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
0
1
2
3
4
5
6
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
A
B
C
D
9
8
7
1
0
NC
V
CC
A
2
3
NC
4
5
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
B
C
NC
D
9
Copyright
2003, Texas Instruments Incorporated
1
SN54HC42, SN74HC42
4 LINE TO 10 LINE DECODERS (1 of 10)
SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003
FUNCTION TABLE
INPUTS
NO.
0
1
2
3
4
5
6
7
8
9
D
L
L
L
L
L
L
L
L
H
H
H
H
Invalid
H
H
H
H
C
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
0
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
2
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
3
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
OUTPUTS
4
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
5
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
6
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
7
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
8
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
9
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
2
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DALLAS, TEXAS 75265
SN54HC42, SN74HC42
4 LINE TO 10 LINE DECODERS (1 of 10)
SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1
15
A
2
1
0
3
2
4
B
14
5
4
3
6
13
C
7
5
6
9
12
D
10
7
8
11
Pin numbers shown are for the D, J, N, NS, and W packages.
9
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SN54HC42, SN74HC42
4 LINE TO 10 LINE DECODERS (1 of 10)
SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HC42
MIN
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
∆t/∆v
Low-level input voltage
Input voltage
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
0
0
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
0
0
NOM
5
MAX
6
SN74HC42
MIN
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
High-level input voltage
Input transition rise/fall time
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = −20
µA
VOH
VI = VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
Ci
VI = VCC or 0
VI = VCC or 0,
IO = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
0.1
0.1
0.1
0.26
0.26
±100
8
10
SN54HC42
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
160
10
MAX
SN74HC42
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
80
10
nA
µA
pF
V
V
MAX
UNIT
4
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SN54HC42, SN74HC42
4 LINE TO 10 LINE DECODERS (1 of 10)
SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
A, B, C, or D
0−9
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
65
18
14
28
8
7
150
30
26
75
15
13
SN54HC42
MIN
MAX
225
45
38
110
22
19
SN74HC42
MIN
MAX
190
38
32
95
19
16
ns
ns
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load
TYP
39
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
In-Phase
Output
Input
VCC
50%
tPLH
50%
10%
tPHL
Out-of-Phase
Output
90%
50%
10%
tf
90%
tr
Input
50%
10%
90%
90%
VCC
50%
10% 0 V
tf
tPLH
50%
10%
90%
tr
50%
0V
tPHL
90%
VOH
50%
10%
VOL
tf
VOH
VOL
LOAD CIRCUIT
tr
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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5
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