SN54HC266, SN74HC266
QUADRUPLE 2 INPUT EXCLUSIVE NOR GATES
WITH OPEN DRAIN OUTPUTS
SCLS135F − DECEMBER 1982 − REVISED AUGUST 2003
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current Inverting Outputs Drive Up To
D
10 LSTTL Loads
Low Power Consumption, 20-µA Max I
CC
D
Typical t
pd
= 10 ns
D
±4-mA
Output Drive at 5 V
D
Low Input Current of 1
µA
Max
1A
1B
1Y
2Y
2A
2B
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3Y
3B
3A
1B
1A
NC
V
CC
4B
1Y
NC
2Y
NC
2A
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
SN54HC266 . . . J OR W PACKAGE
SN74HC266 . . . D, N, OR NS PACKAGE
(TOP VIEW)
SN54HC266 . . . FK PACKAGE
(TOP VIEW)
4A
NC
4Y
NC
3Y
NC − No internal connection
description/ordering information
The ’HC266 devices have four independent 2-input exclusive-NOR gates and feature open-drain outputs. They
perform the Boolean function Y = A
⊗
B or Y = AB + AB in positive logic.
ORDERING INFORMATION
TA
PDIP − N
PACKAGE†
Tube of 25
Tube of 50
−40 C 85°C
−40°C to 85 C
SOIC − D
SOP − NS
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
Reel of 2500
Reel of 250
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
ORDERABLE
PART NUMBER
SN74HC266N
SN74HC266D
SN74HC266DR
SN74HC266DT
SN74HC266NSR
SNJ54HC266J
SNJ54HC266W
SNJ54HC266FK
HC266
SNJ54HC266J
SNJ54HC266W
SNJ54HC266FK
HC266
TOP-SIDE
MARKING
SN74HC266N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
2003, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
2B
GND
NC
3A
3B
1
SCLS135F − DECEMBER 1982 − REVISED AUGUST 2003
SN54HC266, SN74HC266
QUADRUPLE 2 INPUT EXCLUSIVE NOR GATES
WITH OPEN DRAIN OUTPUTS
FUNCTION TABLE
INPUTS
A
L
L
H
H
B
L
H
L
H
OUTPUT
Y
H
L
L
H
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±25
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC266
MIN
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
∆t/∆v
Low-level input voltage
Input voltage
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
0
0
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
0
0
NOM
5
MAX
6
SN74HC266
MIN
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
High-level input voltage
Input transition rise/fall time
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC266, SN74HC266
QUADRUPLE 2 INPUT EXCLUSIVE NOR GATES
WITH OPEN DRAIN OUTPUTS
SCLS135F − DECEMBER 1982 − REVISED AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH
TEST CONDITIONS
VI = VIH or VIL,
VO = VCC
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
Ci
VI = VCC or 0
VI = VCC or 0,
IO = 0
VCC
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
0.01
0.002
0.001
0.001
0.17
0.15
±0.1
0.5
0.1
0.1
0.1
0.26
0.26
±100
2
10
SN54HC266
MIN
MAX
10
0.1
0.1
0.1
0.4
0.4
±1000
40
10
SN74HC266
MIN
MAX
5
0.1
0.1
0.1
0.33
0.33
±1000
20
10
nA
µA
pF
V
UNIT
µA
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tPLH
A or B
Y
4.5 V
6V
2V
tPHL
A or B
Y
4.5 V
6V
2V
tt
Y
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
60
13
10
60
13
10
28
8
6
125
25
23
100
20
17
75
15
13
SN54HC266
MIN
MAX
190
38
32
150
30
25
110
22
19
SN74HC266
MIN
MAX
155
31
26
125
25
21
95
19
16
ns
ns
ns
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance per gate
TEST CONDITIONS
No load
TYP
35
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCLS135F − DECEMBER 1982 − REVISED AUGUST 2003
SN54HC266, SN74HC266
QUADRUPLE 2 INPUT EXCLUSIVE NOR GATES
WITH OPEN DRAIN OUTPUTS
PARAMETER MEASUREMENT INFORMATION
VCC
RL = 1 kΩ
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
In-Phase
Output
VCC
Input
50%
tPLH
50%
0V
tPHL
90%
10%
tPHL
Out-of-Phase
Output
90%
50%
10%
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
tPLH
10%
VOH
50%
10% V
OL
tf
VOH
VOL
LOAD CIRCUIT
VCC
50%
10% 0 V
tf
Input
50%
10%
90%
90%
tr
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
SN74HC266D
SN74HC266DE4
SN74HC266DG4
SN74HC266DR
SN74HC266DRE4
SN74HC266DRG4
SN74HC266DT
SN74HC266DTE4
SN74HC266DTG4
SN74HC266N
SN74HC266NE4
SN74HC266NSR
SN74HC266NSRE4
SN74HC266NSRG4
Status
(1)
Package Type Package Pins Package
Drawing
Qty
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
SO
SO
D
D
D
D
D
D
D
D
D
N
N
NS
NS
NS
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50
50
50
2500
2500
2500
250
250
250
25
25
2000
2000
2000
Eco Plan
(2)
Lead/Ball Finish
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
MSL Peak Temp
(3)
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
(4)
Samples
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
HC266
HC266
HC266
HC266
HC266
HC266
HC266
HC266
HC266
SN74HC266N
SN74HC266N
HC266
HC266
HC266
(1)
The marketing status values are defined as follows:
ACTIVE:
Product device recommended for new designs.
LIFEBUY:
TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND:
Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW:
Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
Addendum-Page 1
Microchip MCU
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