HIGH-SPEED
16K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7026S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 25/35/55ns (max.)
— Commercial: 20/25/35/55ns (max.)
• Low-power operation
— IDT7026S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7026L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7026 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
more than one device
• M/
S
= H for
BUSY
output flag on Master,
M/
S
= L for
BUSY
input on Slave
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• TTL-compatible, single 5V (±10%) power supply
• Available in 84-pin PGA and 84-pin PLCC
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
FUNCTIONAL BLOCK DIAGRAM
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
14
(1,2)
A
13L
A
0L
MEMORY
ARRAY
14
Address
Decoder
A
13R
A
0R
CE
L
ARBITRATION
SEMAPHORE
LOGIC
CE
R
SEM
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs are non-tri-stated push-pull.
M/
S
SEM
R
2939 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC 2939/3
6.17
1
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT7026 is a high-speed 16K x 16 Dual-Port Static
RAM. The IDT7026 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 32-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 750mW of power.
The IDT7026 is packaged in a ceramic 84-pin PGA, and a
84-pin PLCC. Military grade product is manufactured in com-
pliance with the latest revision of MIL-STD-883, Class B,
making it ideally suited to military temperature applications
demanding the highest level of performance and reliability.
PIN CONFIGURATIONS
(1,2)
I/O
4L
I/O
3L
I/O
2L
I/O
0L
SEM
L
GND
R/
L
I/O
5L
I/O
7L
I/O
6L
I/O
1L
A
13L
A
12L
A
11L
A
10L
V
CC
OE
L
W
UB
L
LB
L
CE
L
INDEX
I/O
8L
I/O
9L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
GND
I/O
14L
I/O
15L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
I/O
8R
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IDT7026
J84-1
84-PIN PLCC
TOP VIEW(3)
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
A
9L
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
BUSY
L
GND
M/
S
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
2939 drw 02
54
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O
11R
I/O
15R
I/O
12R
I/O
13R
I/O
14R
GND
CE
R
R/
R
GND
A
13R
A
12R
A
11R
I/O
9R
I/O
10R
SEM
R
A
10R
OE
R
UB
R
LB
R
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.17
A
9R
A
8R
W
2
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D)
(1,2)
63
61
60
58
55
54
51
48
46
45
42
11
I/O
7L
66
I/O
5L
64
I/O
4L
62
I/O
2L
59
I/O
0L
56
OE
L
49
SEM
L
50
LB
L
47
A
12L
44
A
11L
43
A
8L
40
10
I/O
10L
67
I/O
8L
65
I/O
6L
I/O
3L
I/O
1L
57
UB
L
53
CE
L
52
A
13L
A
10L
A
9L
41
A
6L
39
09
I/O
11L
69
I/O
9L
68
GND
V
CC
R/
W
L
A
7L
38
A
5L
37
08
I/O
13L
72
I/O
12L
71
73
33
A
4L
35
A
3L
34
07
I/O
15L
75
I/O
14L
70
V
CC
74
IDT7026
G84-3
84-PIN PGA
TOP VIEW(3)
BUSY
L
32
A
1L
31
A
0L
36
06
I/O
0R
76
GND
77
GND
78
GND
28
M/
S
29
A
2L
30
05
I/O
1R
79
I/O
2R
80
V
CC
A
1R
A
0R
26
BUSY
R
27
04
I/O
3R
81
I/O
4R
83
7
11
12
A
3R
23
A
2R
25
03
I/O
5R
82
1
I/O
7R
2
5
GND
8
GND
10
SEM
R
14
17
20
A
6R
22
A
4R
24
02
I/O
6R
84
3
I/O
9R
I/O
10R
4
I/O
13R
6
I/O
15R
9
R/
15
W
R
UB
R
13
A
12R
16
A
9R
18
A
7R
19
A
5R
21
01
I/O
8R
A
I/O
11R
B
I/O
12R
C
I/O
14R
D
OE
R
E
LB
R
F
CE
R
G
A
13R
H
A
11R
J
A
10R
K
A
8R
L
2939 drw 03
Index
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Busy Flag
Master or Slave Select
Power
Ground
2939 tbl 01
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
CE
L
R/
W
L
OE
L
A
0L
– A
13L
I/O
0L
– I/O
15L
CE
R
R/
W
R
OE
R
A
0R
– A
13R
I/O
0R
– I/O
15R
Grade
Military
Commercial
Ambient
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
2939 tbl 02
SEM
L
UB
L
LB
L
BUSY
L
M/
S
V
CC
SEM
R
UB
R
LB
R
BUSY
R
GND
6.17
3
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs
(1)
Outputs
CE
H
X
L
L
L
L
L
L
X
R/
W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
I/O
8-15
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
High-Z
I/O
0-7
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
Both Bytes Deselected
Mode
Deselected: Power-Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
DATA
OUT
Read Lower Byte Only
High-Z
Outputs Disabled
2939 tbl 03
DATA
OUT
DATA
OUT
Read Both Bytes
NOTE:
1. A
0L
— A
13L
≠
A
0R
— A
13R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
(1)
Inputs
Outputs
CE
H
X
H
X
L
L
R/
W
H
H
OE
L
L
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
I/O
8-15
I/O
0-7
Mode
DATA
OUT
DATA
OUT
Read Data in Semaphore Flag
DATA
OUT
DATA
OUT
Read Data in Semaphore Flag
DATA
IN
DATA
IN
—
—
DATA
IN
DATA
IN
—
—
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
2939 tbl 04
X
X
X
X
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
15
). These eight semaphores are addressed by A
0
- A
2
.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Commercial
Military
–0.5 to +7.0
Unit
V
Terminal Voltage –0.5 to +7.0
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
0 to +70
–55 to +125
–55 to +125
50
RECOMMENDED DC OPERATING
CONDTIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
Typ.
5.0
0
—
—
Max. Unit
5.5
0
6.0
(2)
0.8
V
V
V
V
2939 tbl 06
T
A
T
BIAS
T
STG
I
OUT
–55 to +125
–65 to +135
–65 to +150
50
°C
°C
°C
mA
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
NOTES:
2939 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of V
TERM
> Vcc
+ 0.5V.
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(2)
Max.
V
IN
= 3dv
V
OUT
= 3dv
9
10
Unit
pF
pF
NOTES:
2939 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.17
4
IDT7026S/L
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 5.0V
±
10%)
IDT7026S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
Min.
—
—
—
2.4
Max.
10
10
0.4
—
IDT7026L
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
2939 tbl 08
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= –4mA
NOTE:
1. At Vcc = 2.0V, input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(V
CC
= 5.0V
±
10%)
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
I
SB1
Standby Current
(Both Ports — TTL
Level Inputs)
I
SB2
Standby Current
(One Port — TTL
Level Inputs)
I
SB3
Full Standby Current
(Both Ports — All
CMOS Level Inputs)
Test
Condition
Version
MIL.
COM’L.
MIL.
COM’L.
MIL.
COM’L.
MIL.
COM’L.
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
7026X20
7026X25
Com'l. Only
Typ.
(2)
Max. Typ.
(2)
Max. Unit
—
—
180
180
—
—
30
30
—
—
115
115
—
—
1.0
0.2
—
—
110
110
—
—
315
275
—
—
85
60
—
—
210
180
—
—
15
5
—
—
185
160
170
170
170
170
25
25
25
25
105
105
105
105
1.0
0.2
1.0
0.2
100
100
100
100
345
305
305
265
100
80
85
60
230
200
200
170
30
10
15
5
200
175
170
145
mA
mA
mA
mA
mA
CE
= V
IL
, Outputs Open
SEM
= V
IH
f = f
MAX(3)
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX(3)
CE
"A"
= V
IL
and
CE
"B"
= V
IH(5)
Active Port Outputs Open,
f = f
MAX(3)
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
I
SB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
V
IN
> V
CC
- 0.2V or
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
< 0.2V
Active Port Outputs Open,
f = f
MAX(3)
MIL.
COM’L.
NOTES:
2939 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 5V, T
A
= +25°C, and are not production tested. I
CCDC
= 120mA (Typ.)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1 / t
RC,
and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.17
5
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