128MB, 256MB (x72, SR) PC3200
184-PIN DDR SDRAM UDIMM
DDR SDRAM
DIMM
Features
• JEDEC standard 184-pin, dual in-line memory
module (DDR DIMM)
• Utilizes 400MT/s DDR SDRAM components
• Fast data transfer rates: PC3200
• 128MB (16 Meg x 72) and 256MB (32 Meg x 72)
• V
DD
= V
DD
Q= +2.6V
• V
DDSPD
= +2.3V to +3.6V
• 2.6V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/received
with data—i.e., source-synchronous data capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Selectable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes: 7.8125µs
(256MB) maximum average periodic refresh
interval.
• Serial Presence Detect (SPD) with EEPROM
• Selectable READ CAS latency for maximum
compatibility
• Gold edge contacts
MT5VDDT1672A – 128MB
MT5VDDT3272A – 256MB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1: 184-Pin DIMM (MO-206)
1.25in. (31.75mm)
OPTIONS
MARKING
• Package
184-pin DIMM (standard)
184-Pin DIMM (lead-free)
1
• Memory Clock, Speed, CAS Latency
2
5ns (200MHz), 400MT/s, CL = 3
NOTE:
G
Y
-40B
1. Consult Micron for product availability.
2. CL = Device CAS (READ) Latency
Table 1:
Address Table
128MB
256MB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (32 Meg x 16)
1K (A0–A9)
1 (S0#)
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (16 Meg x 16)
512 (A0–A8)
1 (S0#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef80cb210c, source: 09005aef80cb1ff3
DDA5C16_32x72AG.fm - Rev. C 9/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB (x72, SR) PC3200
184-PIN DDR SDRAM UDIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
128MB
128MB
256MB
256MB
MODULE
CONFIGURATION BANDWITH
16 Meg x 72
16 Meg x 72
32 Meg x 72
32 Meg x 72
3.2 GB/s
3.2 GB/s
3.2 GB/s
3.2 GB/s
MEMORY CLOCK,
DATA RATE
5ns, 400 MT/s
5ns, 400 MT/s
5ns, 400 MT/s
5ns, 400 MT/s
CLOCK LATENCY
(CL -
t
RCD -
t
RP)
3-3-3
3-3-3
3-3-3
3-3-3
PART NUMBER
MT5VDDT1672AG-40B__
MT5VDDT1672AY-40B__
MT5VDDT3272AG-40B__
MT5VDDT3272AY-40B__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT5VDDT3272AG-40BA1.
pdf: 09005aef80cb210c, source: 09005aef80cb1ff3
DDA5C16_32x72AG.fm - Rev. C 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x72, SR) PC3200
184-PIN DDR SDRAM UDIMM
Table 3:
Pin Assignment
(184-Pin DIMM Front)
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
Q
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
DD
Q
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DD
Q
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
NC
DQ48
DQ49
V
SS
CK2#
CK2
V
DD
Q
DQS6
DQ50
DQ51
V
SS
NC
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
Table 4:
Pin Assignment
(184-Pin DIMM Back)
139
V
SS
162 DQ47
NC
140 DQS17/DM8 163
141
A10
164 V
DD
Q
142
CB6
165 DQ52
143 V
DD
Q
166 DQ53
144
CB7
167
NC
145
V
SS
168
V
DD
146 DQ36
169 DQS15/DM6
147 DQ37 170 DQ54
148
V
DD
171 DQ55
149 DQS13/DM4 172 V
DD
Q
150 DQ38
173
NC
151 DQ39 174
DQ60
152
V
SS
175 DQ61
153 DQ44
176
V
SS
154 RAS# 177 DQS16/DM7
155 DQ45 178 DQ62
156 V
DD
Q
179 DQ63
157
S0#
180 V
DD
Q
158
NC
181
SA0
159 DQS14/DM5 182
SA1
160
V
SS
183
SA2
161 DQ46
184 V
DDSPD
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
DNU
V
SS
DQ8
DQ9
DQS1
V
DD
Q
CK1
CK1#
V
SS
DQ10
DQ11
CKE0
V
DD
Q
DQ16
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
93
V
SS
116
V
SS
94
DQ4
117 DQ21
95
DQ5
118
A11
96
V
DD
Q 119 DQS11/ DM2
V
DD
97 DQS9/DM0 120
98
DQ6
121
DQ22
99
DQ7
122
A8
100
V
SS
123
DQ23
101
NC
124
V
SS
102
NC
125
A6
103
NC
126 DQ28
104 V
DD
Q
127 DQ29
105 DQ12
128 V
DD
Q
106
DQ13 129 DQS12/ DM3
107 DQS10/DM1
130
A3
108
V
DD
131 DQ30
109 DQ14
132
V
SS
110 DQ15 133 DQ31
111 DNU
134
CB4
112 V
DD
Q 135
CB5
113
NC
136 V
DD
Q
114 DQ20
137
CK0
115
A12
138 CK0#
Figure 2: 184-Pin DIMM Pinouts
Front View
1.25in. PCB
U1
U2
U3
U4
U5
U6
PIN 1
PIN 52
PIN 53
PIN 92
Back View
No Components This Side of Module
PIN 184
PIN 145
PIN 144
PIN 93
Indicates a V
DD
or V
DDQ
pin
Indicates a V
SS
pin
pdf: 09005aef80cb210c, source: 09005aef80cb1ff3
DDA5C16_32x72AG.fm - Rev. C 9/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x72, SR) PC3200
184-PIN DDR SDRAM UDIMM
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#,
RAS#
CK0, CK0#CK1,
CK1#,
CK2, CK2#
CKE
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Clock: CK and CK# are differential clock inputs. All address
and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers, and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE
POWER-DOWN (row ACTIVE in any device bank). CKE is
synchronous for POWER-DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit
and for disabling the outputs. CKE must be maintained
HIGH throughout read and write accesses. Input buffers
(excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during
SELF REFRESH. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after V
DD
is applied and until CKE is first
brought HIGH. After CKE is brought HIGH, it becomes an
SSTL_2 input only.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command. BA0 and BA1
define which mode register (mode register or extended
mode register) is loaded during the LOAD MODE REGISTER
command.
Serial Presence-Detect Data: SDA is a bidirectional pin used
to transfer addresses and data into and out of the presence-
detect portion of the module.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
63, 65, 154
16, 17, 75, 76, 137, 138
21
Input
157
S0#
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43,
48, 115, 118,
122, 125, 130, 141
A0-A12
Input
91
SDA
Input/
Output
Input
Input
92
181, 182, 183
SCL
SA0–SA2
pdf: 09005aef80cb210c, source: 09005aef80cb1ff3
DDA5C16_32x72AG.fm - Rev. C 9/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB (x72, SR) PC3200
184-PIN DDR SDRAM UDIMM
Table 5:
Pin Descriptions
SYMBOL
DQS0–DQS17
TYPE
Input/
Output
DESCRIPTION
Data Strobe: DQS0-DQS8, Output with READ data, input
with WRITE data. DQS is edge-aligned with READ data,
centered in WRITE data. Used to capture data. Data Mask:
DQS9-DQS17 function as DM0-DM8 to mask WRITE data
when HIGH.
Data I/Os: Data bus.
Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information
PIN NUMBERS
5, 14, 25, 36, 47, 56, 67, 78, 86,
97, 107, 119, 129, 140, 149,
159, 169, 177
2, 4, 6, 8, 12, 13, 19, 20, 23, 24,
28, 31, 33, 35, 39, 40, 53, 55,
57, 60, 61, 64, 68, 69, 72, 73,
79, 80, 83, 84, 87, 88, 94, 95,
98, 99, 105, 106, 109, 110, 114,
117, 121, 123, 126, 127, 131,
133, 146, 147, 150, 151, 153,
155, 161, 162, 165, 166, 170,
171, 174, 175, 178, 179
44, 45, 49, 51, 134, 135, 142,
144
1
15, 22, 30, 54, 62, 77, 96, 104,
112, 128, 136, 143, 156, 164,
172, 180
7, 38, 46, 70, 85, 108, 120, 148,
168
3, 11, 18, 26, 34, 42, 50, 58, 66,
74, 81, 89, 93, 100, 116, 124,
132, 139, 145, 152, 160, 176
184
9, 71, 82, 90, 101, 102, 103,
113, 158, 163, 167, 173
10, 111
DQ0–DQ63
Input/
Output
CB0–CB7
V
REF
V
DD
Q
Input/
Output
Input
Supply
Check Bits: ECC 1-bit error detection and correction.
SSTL_2 reference voltage.
DQ Power Supply: +2.6V ±0.1V.
V
DD
V
SS
Supply
Supply
Power Supply: +2.6V ±0.1V.
Ground.
V
DDSPD
NC
DNU
Supply
–
–
Serial EEPROM positive power supply: +2.3V to +3.6V.
No Connect: These pins should be left unconnected.
Do Not Use: These pins are not connected on this module
but are assigned pins on other modules in this product
family.
pdf: 09005aef80cb210c, source: 09005aef80cb1ff3
DDA5C16_32x72AG.fm - Rev. C 9/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
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