256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
Smart ZBT™ Feature
2.5V or 3.3V I/O, Burst Counter
Pipelined Outputs
x
x
Preliminary
IDT71V656
IDT71V658
Features
256K x 36, 512K x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Smart ZBT
TM
Feature - Eases system timing requirements
and reduces the likelihood of bus contention
With Smart ZBT
TM
the output turn-on (t
CLZ
) is adaptable to
the user's system and is a function of the cycle time.
Backward compatable with IDT’s existing ZBT offerings.
User selectable Smart ZBT
TM
or Original ZBT
TM
mode pin (M
S
)
M
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
W
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
BW
Three chip enables for simple depth expansion
3.3V power supply (±5%)
User selectable 3.3V or 2.5V I/O Supply (V
DDQ)
Packaged in a JEDEC standard 100-lead plastic thin quad
flatpack (TQFP) and 119-lead ball grid array (BGA).
Description
The IDT71V656/58 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs. They are designed to eliminate
dead bus cycles when turning the bus around between reads and
writes, or writes and reads. Thus, they have been given the name
ZBT
TM
, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V656/58 offer the user an optional Smart functionality
which simplifies system timing requirements when turning the bus around
between writes and reads. Traditionally, SRAMs are designed with
fast turn-on times (t
CLZ
) in order to meet the requirements of high
speed applications. This fast turn-on may lead to bus contention at
slower speeds, i.e. 133 MHz and slower, since these designs
oftentimes use less aggressive ASICs/controllers with loose turn-off
parameters (t
CHZ
). Thus at slower speeds, more margin on the
RAM’s t
CLZ
may be needed to compensate for the slow turn-off of the
ASIC/controller. The IDT71V656/58 have the ability to provide this
extra margin by allowing t
CLZ
to adapt to the user’s system.
With the Smart ZBT
TM
feature, the output turn-on time (t
CLZ
) adapts to
the user’s system and is solely a function of cycle time (t
CYC
). Thus
with Smart ZBT
TM
, t
CLZ
is independent of process, voltage, and
temperature variations. With this deterministic output turn-on fea-
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Pin Description Summary
A
0
-A
18
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
M
S
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Data Input / Output
Core Power, I/O Power
Ground
Sm art ZBT™ Mode Enable
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Input
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Synchronous
Static
Static
Static
5000 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
Smart ZBT and Smart Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is also supported by Micron Technology, Inc.
OCTOBER 1999
DSC-5000/04
1
©1999 Integrated Device Technology, Inc.
IDT71V656, IDT71V658, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V or 3.3V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Description (cont.)
ture, the guesswork of when the SRAM begins to drive the bus is
removed, therefore easing system timing requirements. The Smart
feature allows the turn-on time of the ZBT
TM
SRAM output drivers
(t
CLZ
) to adapt to match the requirements of the system.
The IDT71V656/58 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V656/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold their
previous values.
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the
user to deselect the device when desired. If any one of these three
is not asserted when ADV/LD is low, no new memory operation can
be initiated. However, any pending data transfers (reads or writes)
will be completed. The data bus will tri-state two cycles after chip is
deselected or a write is initiated.
The IDT71V656/58 have an on-chip burst counter. In the burst
mode, the IDT71V656/58 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO
input pin. The
LBO
pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst
counter (ADV/LD = HIGH).
The IDT71V656/58 SRAMs utilize IDT’s latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-lead thin plastic quad flatpack (TQFP) as well as a 119-lead ball grid
array (BGA).
Pin Definitions
(1)
Symbol
A
0
-A
18
ADV/LD
Pin Function
Address Inputs
Advance / Load
I/O
I
I
Active
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD
low,
CEN
low, and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is
sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any
burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced for any
burst that was in progress. The external addresses are ignored when ADV/LD is sampled high.
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
Synchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous inputs, including clock are ignored
and outputs remain unchanged. The effect of
CEN
sampled high on the device outputs is as if the low to high clock
transition did not occur. For normal operation,
CEN
must be sampled low at rising edge of clock.
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(when R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
1
-BW
4
) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is sampled
high. The appropriate byte(s) of data are written into the device two cycles later.
BW
1
-BW
4
can all be tied low if
always doing write to the entire 36-bit word.
Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the IDT71V656/58 (CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBT
TM
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip. CE
2
has inverted polarity
but otherwise identical to
CE
1
and
CE
2
.
This is the clock input to the IDT71V656/58. Except for
OE,
all timing references for the device are made with respect
to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered
by the rising edge of CLK.
Burst order selection input. When
LBO
is high the Interleaved burst sequence is selected. When
LBO
is low the
Linear burst sequence is selected.
LBO
is a static input and it must not change during device operation.
Asynchronous output enable.
OE
must be low to read data from the 71V656/58. When
OE
is high the I/O pins are
in a high-impedance state.
OE
does not need to be actively controlled for read and write cycles. In normal operation,
OE
can be tied low.
Smart ZBT™ mode enable input. When
Ms
is low the Smart ZBT™ mode is selected. When
Ms
is high the original
ZBT™ mode is selected.
Ms
is a static input and it must not change during device operation.
3.3V core power supply.
User selectable 3.3V or 2.5V I/O Supply.
Ground.
5000 tbl 02
R/W
CEN
Read / Write
Clock Enable
I
I
N/A
LOW
BW
1
-BW
4
Individual Byte
Write Enables
I
LOW
CE
1
,
CE
2
Chip Enables
I
LOW
CE
2
CLK
I/O
0
-I/O
31
I/O
P1
-I/O
P4
LBO
OE
Chip Enable
Clock
Data Input/Output
Linear Burst Order
Output Enable
I
I
I/O
I
I
HIGH
N/A
N/A
LOW
LOW
Ms
V
DD
V
DDQ
V
SS
Output Enable
Power Supply
Power Supply
Ground
I
N/A
N/A
N/A
LOW
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V656, IDT71V658, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V or 3.3V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Functional Block Diagram
Ms
LBO
Address A [0:17]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
Control
D
Q
256Kx36 BIT
MEMORY ARRAY
Address
Input Register
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5000 drw 01a
,
Data I/O [0:31],
I/O P[1:4]
Ms
LBO
Address A [0:18]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
D
Clk
D
Q
D
Q
512Kx18 BIT
MEMORY ARRAY
Address
Control
Input Register
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5000 drw 01
,
Data I/O [0:15],
I/O P[1:2]
6.42
3
IDT71V656, IDT71V658, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V or 3.3V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Recommended DC Operating
Conditions with V
DDQ
at 2.5V
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
2.375
0
1.7
1.7
-0.3
(1)
Typ.
3.3
2.5
0
____
____
____
Recommended DC Operating
Conditions with V
DDQ
at 3.3V
Unit
V
V
V
V
V
V
5000 tbl 03
Max.
3.465
2.625
0
V
DD
+0.3
V
DDQ
+0.3
0.7
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
3.135
3.135
0
2.0
2.0
-0.3
(1)
Typ.
3.3
3.3
0
____
____
____
Max.
3.465
3.465
0
V
DD
+0.3
V
DDQ
+0.3
0.8
Unit
V
V
V
V
V
V
5000 tbl 04
NOTE:
1. V
IL
(min.) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
NOTE:
1. V
IL
(min.) = –1.0V for pulse width less than t
CYC
/2, once per cycle.
Recommended Operating
Temperature and Supply Voltage
G rade
C om m ercial
C om m ercial
Temperature
0° C to + 70° C
0° C to + 70° C
V
SS
0V
0V
V
DD
3.3V ± 5%
3.3V ± 5%
V
DDQ
2.5V ± 5%
V
DD
5000 tbl 05
Pin Configuration - 256K x 36
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
M
s
V
DD
V
DD
(1)
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5000 drw 02
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
A
17
A
8
A
9
A
6
A
7
CE
1
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
(1)
V
DD
V
SS
(4)
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
Mode
Smart ZBT
TM
Original ZBT
TM
Ms
V
SS
V
DD
5000 tb l 05a
NOTES:
1. Pins 16 and 66 do not have to be connected directly to V
DD
as long as the input voltage is
≥
V
IH
.
2. Pin 84 is reserved for a future 16M.
3. DNU = Do not use
4. Pin 64 does not have to be connected directly to V
SS
as long as the input voltage is
≤
V
IL
.
6.42
4
LBO
A
5
A
4
A
3
A
2
A
1
A
0
DNU
(3)
DNU
(3)
V
SS
V
DD
DNU
(3)
DNU
(3)
A
10
A
11
A
12
A
13
A
14
A
15
A
16
,
Top View
TQFP
IDT71V656, IDT71V658, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
Smart ZBT™ Feature, 2.5V or 3.3V I/O, Burst Counter, and Pipelined Outputs
Preliminary
Commercial Temperature Ranges
Pin Configuration - 512K x 18
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
A
18
A
8
A
9
A
6
A
7
CE
1
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
V
TERM
(3,6)
V
TERM
(4,6)
V
TERM
(5,6)
T
A
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Commercial
-0.5 to +4.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
0 to +70
-55 to +125
-55 to +125
2.0
50
Unit
V
V
V
V
o
o
o
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DDQ
V
SS
NC
NC
I/O
8
I/O
9
V
SS
V
DDQ
I/O
10
I/O
11
M
S
V
DD
V
DD
(1)
V
SS
I/O
12
I/O
13
V
DDQ
V
SS
I/O
14
I/O
15
I/O
P2
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
NC
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
(1)
V
DD
V
SS
(4)
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
5000 drw 02a
C
C
C
W
mA
5000 tbl 06
,
NOTES:
1. Pins 16 and 66 do not have to be connected directly to V
DD
as long as the input
voltage is
≥
V
IH
.
2. Pin 84 is reserved for a future 16M.
3. DNU = Do not use
4. Pin 64 does not have to be connected directly to V
SS
as long as the input voltage is
≤
V
IL
.
Top View
TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V
DDQ
during power
supply ramp up.
LBO
A
5
A
4
A
3
A
2
A
1
A
0
DNU
(3)
DNU
(3)
V
SS
V
DD
DNU
(3)
DNU
(3)
A
11
A
12
A
13
A
14
A
15
A
16
A
17
Mode
Smart ZBT
TM
Ms
V
SS
V
DD
5000 tb l 05a
(T
A
= +25°C, f = 1.0MHz, TQFP Package)
Symbol
C
IN
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
5000 tbl 07
Capacitance
Original ZBT
TM
C
I/O
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
5
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